The industry standard Two-Wire timing diagram is shown in Figure 4-1, with the timing diagram definitions in Table 4-1. The key operating states are:
- Bus Idle: Both SDA and SCL lines remain high.
- START Condition: A START condition is defined by a change from high to low in the state of the SDA line, while the SCL line is high. Each data transfer is initiated with a START condition (see Figure 4-1).
- STOP Condition: A STOP condition is defined by a change from low to high in the state of the SDA line, while the SCL line is high. Each data transfer is terminated with a repeated START or STOP condition (see Figure 4-1).
- Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of each 8-bit byte of data.
- Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device acknowledges by pulling down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the master may terminate the transaction by generating a Not Acknowledge on the last byte that has been transmitted by the slave (see Figure 4-2).
Table 4-1 Two-Wire Timing Diagram DefinitionsParameter | Min | Max | Units |
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SCL Operating Frequency | fSCL | 1 | 400 | kHz |
Bus Free Time Between STOP and START Conditions | tBUF | 600 | | ns |
Hold Time After Repeated START Condition. After this period, the first clock is generated. | tHDSTA | 600 | | ns |
Repeated START Condition Setup Time | tSUSTA | 600 | | ns |
STOP Condition Setup Time | tSUSTO | 600 | | ns |
Data Hold Time | tHDDAT | 0 | | ns |
Data Setup Time | tSUDAT | 100 | | ns |
SCL Clock LOW Period | tLOW | 1300 | | ns |
SCL Clock HIGH Period | tHIGH | 600 | | ns |
Clock/Data Fall Time | tF | | 300 | ns |
Clock/Data Rise Time | tR | | 300 | ns |