SBOU024C august   2004  – july 2023 PGA309

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     If You Need Assistance
    4.     Information About Cautions and Warnings
    5.     FCC Warning
    6.     Trademarks
  3. 1Introduction
    1. 1.1  PGA309 Functional Description
    2. 1.2  Sensor Error Adjustment Range
    3. 1.3  Gain Scaling
    4. 1.4  Offset Adjustment
    5. 1.5  Voltage Reference
    6. 1.6  Sensor Excitation and Linearization
    7. 1.7  ADC for Temperature Sensing
    8. 1.8  External EEPROM and Temperature Coefficients
    9. 1.9  Fault Monitor
    10. 1.10 Over-Scale and Under-Scale Limits
    11. 1.11 Power-Up and Normal Operation
    12. 1.12 Digital Interface
    13. 1.13 Pin Configuration
  4. 2Detailed Description
    1. 2.1  Gain Scaling
      1. 2.1.1 PGA309 Transfer Function
      2. 2.1.2 Solving For Gain Settings
    2. 2.2  Offset Scaling
    3. 2.3  Zero DAC and Gain DAC Architecture
    4. 2.4  Output Amplifier
    5. 2.5  Reference Voltage
    6. 2.6  Linearization Function
      1. 2.6.1 System Definitions
      2. 2.6.2 Key Linearization Design Equations
        1. 2.6.2.1 Lin DAC Counts Conversion
      3. 2.6.3 Key Ideal Design Equations
        1. 2.6.3.1 Linearization Design
        2.       37
    7. 2.7  Temperature Measurement
      1. 2.7.1 Temp ADC Start-Convert Control
      2. 2.7.2 External Temperature Sensing with an Excitation Series Resistor
    8. 2.8  Fault Monitor
    9. 2.9  Over-Scale and Under-Scale
      1. 2.9.1 Over-Scale and Under-Scale Calculation
      2.      44
    10. 2.10 Noise and Coarse Offset Adjust
    11. 2.11 General AC Considerations
  5. 3Operating Modes
    1. 3.1 Power-On Sequence and Normal Stand-Alone Operation
    2. 3.2 EEPROM Content and Temperature Lookup Table Calculation
      1. 3.2.1 Temperature Lookup Table Calculation
        1. 3.2.1.1 Temperature Lookup Table Calculation
        2.       52
        3.       53
    3. 3.3 Checksum Error Event
    4. 3.4 Test Pin
    5. 3.5 Power-On Initial Register States
      1. 3.5.1 PGA309 Power-Up State
  6. 4Digital Interface
    1. 4.1  Description
    2. 4.2  Two-Wire Interface
      1. 4.2.1 Device Addressing
      2. 4.2.2 Two-Wire Access to PGA309
    3. 4.3  One-Wire Interface
    4. 4.4  One-Wire Interface Timeout
    5. 4.5  One-Wire Interface Timing Considerations
    6. 4.6  Two-Wire Access to External EEPROM
    7. 4.7  One-Wire Interface Initiated Two-Wire EEPROM Transactions
    8. 4.8  PGA309 Stand-Alone Mode and Two-Wire Transactions
    9. 4.9  PGA309 Two-Wire Bus Master Operation and Bus Sharing Considerations
    10. 4.10 One-Wire Operation with PRG Connected to VOUT
    11. 4.11 Four-Wire Modules and One-Wire Interface (PRG)
  7. 5Application Background
    1. 5.1 Bridge Sensors
    2. 5.2 System Scaling Options for Bridge Sensors
      1. 5.2.1 Absolute Scale
      2. 5.2.2 Ratiometric Scale
    3. 5.3 Trimming Real World Bridge Sensors for Linearity
    4. 5.4 PGA309 Calibration Procedure
  8. 6Register Descriptions
    1. 6.1 Internal Register Overview
    2. 6.2 Internal Register Map
      1. 6.2.1 Register 0: Temp ADC Output Register (Read Only, Address Pointer = 00000)
      2. 6.2.2 Register 1: Fine Offset Adjust (Zero DAC) Register (Read/Write, Address Pointer = 00001)
      3. 6.2.3 Register 2: Fine Gain Adjust (Gain DAC) Register (Read/Write, Address Pointer = 00010)
      4. 6.2.4 Register 3: Reference Control and Linearization Register (Read/Write, Address Pointer = 00011)
      5. 6.2.5 Register 4: PGA Coarse Offset Adjust and Gain Select/Output Amplifier Gain Select Register (Read/Write, Address Pointer = 00100)
      6. 6.2.6 Register 5: PGA Configuration and Over/Under-Scale Limit Register (Read/Write, Address Pointer = 00101)
      7. 6.2.7 Register 6: Temp ADC Control Register (Read/Write, Address Pointer = 00110)
      8. 6.2.8 Register 7: Output Enable Counter Control Register (Read/Write, Address Pointer = 00111)
      9. 6.2.9 Register 8: Alarm Status Register (Read Only, Address Pointer = 01000)
  9.   A External EEPROM Example
    1.     A.1 PGA309 External EEPROM Example
      1.      A.1.1 Gain and Offset Scaling for External EEPROM
      2.      94
  10.   B Detailed Block Diagram
    1.     B.1 Detailed Block Diagram
  11.   C Glossary
  12.   Revision History

2.1 Gain Scaling

The PGA309 contains three main gain blocks for scaling differential input bridge sensor signals, as shown in Figure 2-1. The Front-End PGA contains the highest gain selection to allow for the highest signal-to-noise ratio by applying the largest gain at the front of the signal chain before the addition of other noise sources. The Front-End PGA gain select has eight gain settings (4, 8, 16, 23.27, 32, 42.67, 64, and 128) and is set by Register 4 bits (11:8). Bit 11 selects the polarity of the input mux.

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VOUT = [(VDIFF + VCOARSE OFFSET)(Front-End PGA Gain) + VZERO DAC][Gain DAC][Output Amplifier Gain]
Figure 2-1 Gain Blocks of the PGA309

The Front-End PGA is followed by the Gain DAC. The fine gain adjust is controlled by the 16-bit Gain DAC and is adjustable from 0.3333 to 1. Register 2 is used only for the Gain DAC setting.

Final signal gain is applied through the Output Amplifier, which has an internal select of seven gain settings (2, 2.4, 3, 3.6, 4.5, 6, 9). The Output Amplifier has a selection to disable the internal gain and allow user-supplied external resistors to set the Output Amplifier gain. Register 4 bits (14:12) select the internal Output Amplifier gains, except when programmed with ‘111’ when the internal feedback is disabled. The combined gain blocks allow for a VOUT/VDIFF signal gain of 2.666 (400kHz bandwidth) to 1152 (60kHz bandwidth).

The Front-End PGA of the PGA309 is a three op amp instrumentation amplifier for optimum rejection of common-mode voltages. This instrumentation amplifier is constructed using op amps with auto-zero front-ends to virtually eliminate 1/f noise.

As with any instrumentation amplifier, there are limitations on the output voltage swing and input common-mode voltage range. The circuit in Figure 2-2 is representative of the Front-End PGA inside of the PGA309 and is used to evaluate critical internal node voltages to ensure that output voltage swing and common-mode limits are not violated. It is possible to violate the limits of these internal nodes and still have apparently valid output voltages at VOUT of the PGA309. There are internal comparators that can be set to monitor these internal nodes to indicate an out-of-limit condition during sensor calibration (see Section 2.8, Fault Monitor).

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A. Input mux allows for sensor output polarity reversal.
B. PGA difference amplifier gain of 4 allows full range out of Zero DAC and full voltage swing out of A1 and A2 without common-mode violation on A3 input.
Figure 2-2 Front-End PGA Gain—Internal Node Calculations

After choosing appropriate scaling for the PGA309 gain blocks, a simple hand analysis can check for internal node limit violations. It is important to convert the PGA309 input voltages (VINP, VINN) to common-mode and differential components for the maximum sensor output. The model for this conversion is illustrated in Figure 2-2. The Front-End PGA has a gain of 4 in difference amplifier A3. To analyze important internal nodes VOA1 and VOA2, it is necessary to assign the proper gain factor (G) to op amps A1 and A2. This is detailed in Figure 2-2 with the respective equations for the output voltages shown at the appropriate nodes. For maximum VDIFF output of the sensor, VOA1 and VOA2 are within the allowed voltage swing of: 0.1V < (VOA1 or VOA2) < VS − 0.12. Or, for this example: 0.1V < (VOA1 or VOA2) < 4.88V.

Other applications may yield different results that require different gain scaling or a resistor in the positive or negative leg of the sensor excitation path to adjust the common-mode input voltage of the PGA309. The maximum allowable input voltage range (IVR) of the PGA309 is specified as 0.2V < IVR < VSA − 1.5V, which for this application translates to 0.2V < IVR < 3.5V. In Figure 2-2 we see VINP = 2.550V and VINN = 2.450V, which is within the acceptable IVR specification.

The output (VFRONT) of difference amplifier A3 has a gain of 4 in it for voltages out of A2 and A1, but a gain of 1 for voltages out of the Zero DAC. VFRONT is shown with the contribution from VDIFF times the Front-End PGA gain plus the Zero DAC output voltage. The VFRONT signal is further processed through the Gain DAC and Output Amplifier gain blocks.

Figure 2-3 depicts the Gain DAC and Output Amplifier gain blocks inside the PGA309. For this example the Gain DAC was set to 0.859475571 and the Output Amplifer to a gain of 2. As shown in Figure 2-3, the net output voltage, VOUT, is 4.5V for the maximum VDIFF output of the sensor.

For VOUT MIN, the sensor output of 0V:

VOUT MIN = VZERO DAC [(Gain DAC)(Output Amplifier Gain)]

For this example:

VOUT MIN = 0.290908813V [(0.859475571)(2)] = 0.5000V

The Output Amplifier has external connections, which allow the end-user maximum flexibility in Output Amplifier configurations for a variety of applications. The use of the VFB and VSJ pins, are described in Section 2.4, Output Amplifier.

Example2-1 shows the procedure for solving for gain settings.

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VOUT = [(VDIFF + VCOARSE OFFSET)(Front-End PGA Gain) + VZERO DAC][Gain DAC][Output Amplifier Gain]
Figure 2-3 Fine Gain Adjust of the PGA309