SBOU282A December   2022  – March 2023 OPA928

 

  1.   Abstract
  2.   Trademarks
  3. 1Read This First
    1. 1.1 EVM Cleanliness Guidelines
  4. 2Overview
    1. 2.1 Guarding and Shielding
  5. 3Getting Started
    1. 3.1 Related Documentation From Texas Instruments
    2. 3.2 Electrostatic Discharge Caution
  6. 4EVM Circuit Description
    1. 4.1 High-Impedance Amplifier Circuit
    2. 4.2 Transimpedance Amplifier Circuit
      1. 4.2.1 Configure the TIA
      2. 4.2.2 TIA Functions
        1. 4.2.2.1 T-Switch
        2. 4.2.2.2 Guarded Diode Limiter
  7. 5Cleaning the EVM
    1. 5.1 Ultrasonic Wash
    2. 5.2 Manual Cleaning Procedure
  8. 6Schematic, PCB Layout, and Bill of Materials
    1. 6.1 EVM Schematic
    2. 6.2 PCB Layout
    3. 6.3 Bill of Materials

4.2.1 Configure the TIA

The TIA is configured through the pin sockets, or by installing and removing jumpers across certain jumper blocks. JP2 and JP3 are separated into single-pin jumper blocks JP2a/JP2b and JP3a/JP3b. Separating these jumper blocks prevents current from leaking through the jumper block material when the jumpers are uninstalled, and allows space for guard copper between the output and any disconnected feedback components. A special length shunt jumper is included in the EVM to connect across JP2 or JP3. The default configuration installs the shunt jumper at JP2, placing the 10-GΩ resistor in the feedback path.

Terminal block J7 and jumper block JP4 control the additional functions described in Section 4.2.2.

Table 4-1 lists the components and connections associated with each jumper block.

Table 4-1 TIA Jumper Block Connections
DesignatorComponentConnection With Jumper Shunt Installed
JP2a/JP2bRF (10 GΩ)RF in series between IN– and Vout (TIA configuration)
JP3a/JP3bCF (100 pF)CF in series between IN– and Vout (integrator configuration)
JP4D1D1 in series between Vout and Guard. Limits output voltage. See Section 4.2.2.2
J7K1, K2Drives K1, K2 MOS FET relays to discharge feedback. See Section 4.2.2.1

Pin sockets allow easy configuration with through-hole components, such as photodiodes at the input or large value resistors in the feedback path. P3 is a surface-mounted pin socket array that allows through-hole sensors of various sizes to be easily configured at the input. P3 can be driven by the Sensor Bias terminal located at J9.

Table 4-2 lists the nodes associated with each pin socket.

Table 4-2 TIA Pin Socket Configurations
DesignatorNode
P1, P2Inverting Input (U2)
P3Sensor Bias (J9)
P4, P5Vout (U2)
P6, P7Analog Ground (GND)