SBOU296A April   2023  – September 2023 PGA855

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Related Documentation
    2. 1.2 Electrostatic Discharge Caution
    3. 1.3 Hot Surface Warning
  5. 2EVM Circuit Description
  6. 3Jumper Settings
  7. 4Power-Supply Connections
  8. 5Analog Input and Output Connections
  9. 6Digital Input Pins and Gain Control
  10. 7Modifications
  11. 8Schematic, PCB Layout, and Bill of Materials
    1. 8.1 Schematic
    2. 8.2 PCB Layout
    3. 8.3 Bill of Materials
  12. 9Revision History

4 Power-Supply Connections

The PGA855EVM uses two sets of voltage supplies: input stage and output stage. The device operates using input-stage power supplies from ±4 V (8 V) to ±18 V (36 V) and output-stage power supplies from ±2.25 V (4.5 V) to ±18 V (36 V). The output-stage supply voltage must not exceed the input-stage supply voltage.

The input-stage power-supply connections for the PGA855EVM are provided through connector J13 at the top of the EVM. The input-stage positive power-supply connection is labeled +VCC, the negative power-supply connection is labeled –VEE, and the ground connection is labeled GND. To connect power to the PGA855EVM, insert wires into each terminal of J13 and then tighten the screws to make the connection. Table 6-2 summarizes the pin definition for supply connector J1 and the allowed voltage range for each supply connection.

Table 4-1 PGA855EVM Supply-Range Specifications
Connector Pin Number Supply Connection Voltage Range
J13.3 Input-stage positive supply (+VCC) Single supply, VS = +VCC: 8 V to 36 V
Dual supply, VS = (+VCC) – (–VEE): 4 V to 18 V
J13.2 Ground 0 V
J13.1 Negative supply (–VEE) Single supply, VS = +VCC: 0 V (GND)
Dual supply, VS = (+VCC) – (–VEE): –4 V to –18 V
J14.1

LVDD+_ext

 Single supply, LVDD+_ext: 4.5 V to 36 V
Dual supply, output stage supply (LVSS+) – (LVSS–): 2.25 V to 18 V
J14.2 Ground 0 V
J14.3 LVSS–_ext Single supply, LVSS–_ext: 0 V (GND)
Dual supply, output stage supply (LVSS+) – (LVSS–): –2.25 V to –18 V
J14.4 Ground 0 V

By default, the output-stage supply-voltage levels (+LVDD and –LVSS) are set to the PGA855 positive (+VCC) and negative (–VEE) supplies, respectively. The +LVDD pin is connected to +VCC through jumper J9 1-2, and the –LVSS pin is connected to –VEE through J16 1-2. Screw terminal connector J14 provides access to the output-stage supply pins. To set the voltage level of LVDD and LVSS with an external supply, shunt jumper J9 2-3 to access the +LVDD using connector J14.1. In a similar fashion, shunt jumper J16 2-3 to access the –LVSS pin using connector J14.3.

Figure 4-1 shows the PGA855EVM voltage supply connections.

GUID-20230403-SS0I-Z2DW-X9X7-RNGGHZVVK6CZ-low.svgFigure 4-1 PGA855EVM Voltage Supply Connections