SBOU296A April   2023  – September 2023 PGA855

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Related Documentation
    2. 1.2 Electrostatic Discharge Caution
    3. 1.3 Hot Surface Warning
  5. 2EVM Circuit Description
  6. 3Jumper Settings
  7. 4Power-Supply Connections
  8. 5Analog Input and Output Connections
  9. 6Digital Input Pins and Gain Control
  10. 7Modifications
  11. 8Schematic, PCB Layout, and Bill of Materials
    1. 8.1 Schematic
    2. 8.2 PCB Layout
    3. 8.3 Bill of Materials
  12. 9Revision History

6 Digital Input Pins and Gain Control

The PGA855 provides eight binary gain settings, from an attenuating gain of 0.125 V/V to a maximum of 16 V/V. The gain is controlled by three digital selection pins: A0, A1, and A2. By default, the PGA855 is configured to a gain of 0.125 V/V.

The evaluation board provides shunt jumpers J10, J11, and J12 to set the PGA855 gain-control selection pins. Table 6-2 lists the gain-control options. To set the gain-control pin high, install the shunt on the corresponding jumper. To set the gain-control pin low, remove the shunt jumper.

Table 6-1 PGA855EVM Gain Control

A2

Jumper J10

Connector J15.1

A1

Jumper J11

Connector J15.2

A0

Jumper J12

Connector J15.3

PGA Gain (V/V)
Low (Open) Low (Open) Low (Open) 0.125
Low (Open) Low (Open) High (Shunt) 0.25
Low (Open) High (Shunt) Low (Open) 0.5
Low (Open)

High (Shunt)

 High (Shunt) 1
High (Shunt)

Low (Open)

 Low (Open) 2
High (Shunt) Low (Open) High (Shunt) 4
High (Shunt)

High (Shunt)

 Low (Open) 8
High (Shunt) High (Shunt) High (Shunt) 16

Alternatively, the A0, A1, and A2 digital pins can be driven externally through connector J15. Any pin that is not driven by an external source, or any shunt that is left open, is biased at DGND using pulldown resistors. Figure 6-1 shows the gain-setting block diagram.

GUID-20230403-SS0I-BD6F-VPTT-LFPRZBRMWL3L-low.svg Figure 6-1 PGA855EVM Gain Control