SBOU302A June   2023  – December 2023 INA740A , INA740B , INA745A , INA745B , INA780A , INA780B

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Quick Start Setup
    2. 2.2 EVM Operation
      1. 2.2.1 Current Sensing Operation
        1. 2.2.1.1 Detailed Setup
    3. 2.3 Circuitry
      1. 2.3.1 Current Sensing IC
      2. 2.3.2 Input Signal Path
      3. 2.3.3 Digital Circuitry
        1. 2.3.3.1 I2C
    4.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  7. 3Software
    1. 3.1 Setup
      1. 3.1.1 Driver Installation
      2. 3.1.2 Firmware
        1. 3.1.2.1 Firmware Debug
      3. 3.1.3 GUI Setup and Connection
        1. 3.1.3.1 Initial Setup
        2. 3.1.3.2 GUI to EVM Connection
    2. 3.2 GUI Operation
      1. 3.2.1 Homepage Tab
      2. 3.2.2 Registers Tab
      3. 3.2.3 Results Data Tab
    3. 3.3 Direct EVM USB Communication
      1. 3.3.1 Standard USB Read and Write Operations
      2. 3.3.2 Collect Data Through the USB BULK Channel
  8. 4Hardware Design Files
    1. 4.1 Schematics
      1. 4.1.1 SENS108 (INA740AEVM, INA740BEVM, INA741EVM)
      2. 4.1.2 SENS109 (INA745AEVM, INA745BEVM, INA746EVM)
      3. 4.1.3 SENS119 (INA780AEVM, INA780BEVM, INA781EVM)
    2. 4.2 PCB Layout
      1. 4.2.1 SENS108 (INA740AEVM, INA740BEVM, INA741EVM)
      2. 4.2.2 SENS109 (INA745AEVM, INA745BEVM, INA746EVM)
      3. 4.2.3 SENS119 (INA780AEVM, INA780BEVM, INA781EVM)
    3. 4.3 Bill of Materials
      1. 4.3.1 SENS108 (INA740-INA741EVM), SENS109 (INA745-INA746EVM), SENS119 (INA780-INA781EVM)
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Related Documentation
  11. 7Revision History

4.2 PCB Layout

All boards are designed with following parameters:

  • 8 mil minimum trace width
  • 5 mil minimum clearance
  • 5 mil minimum annular ring
  • 8 mil spacing between IS+ and IS- pours
  • 4 signal layers, each layer is 2 oz copper
  • Dielectric layers are 17 mil thick
  • All vias in proximity to U1 are tented
Note: Board layouts are not to scale. These figures are intended to show how the board is laid out. The figures are not intended to be used for manufacturing EVM PCBs.