SBVA092 June   2022 TPS7A14

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 TPS7A14 Functional Block Diagram
    2. 1.2 Biasing Rail for NMOS LDO
  4. 2Design and Considerations to Check
    1. 2.1 Configuring External Resistor Network
    2. 2.2 Feed-forward Capacitor for Loop Stability
    3. 2.3 IR Drop Compensation by Remote_Sense
  5. 3Stability Verification
    1. 3.1 Simulated Bode Plot vs. Evaluated Bode Plot
    2. 3.2 Transient Response in Time Domain
  6. 4Summary
  7. 5References

3.2 Transient Response in Time Domain

Figure 3-3 shows that added CFF can improve the load transient performance. The amount of ripple tells the improvement. Test condition has a transient of 10 mA to 1.0 A and A/us slew rate. It can be left for further tune by users.

GUID-20220603-SS0I-XK29-QSDX-1SSSNRZF7PP3-low.png Figure 3-3 Load Transient Performance Comparison
GUID-20220603-SS0I-2CBR-S9VJ-94HLXLL0R6FS-low.png Figure 3-4 Transient Response of Modified Vout=1.2 V (with 10 nF Cff)