SBVA092 June   2022 TPS7A14

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 TPS7A14 Functional Block Diagram
    2. 1.2 Biasing Rail for NMOS LDO
  4. 2Design and Considerations to Check
    1. 2.1 Configuring External Resistor Network
    2. 2.2 Feed-forward Capacitor for Loop Stability
    3. 2.3 IR Drop Compensation by Remote_Sense
  5. 3Stability Verification
    1. 3.1 Simulated Bode Plot vs. Evaluated Bode Plot
    2. 3.2 Transient Response in Time Domain
  6. 4Summary
  7. 5References

2.1 Configuring External Resistor Network

As shown in Section 1.2, users can configure external resistor network providing scaled Vout information into feedback control loop. To modify fixed programmed Vout for variable power rails, set one reference device. This note deals building 1.2 V output from TPS7A1408. As stated in previous Section 1.1, TPS7A14 has a unit gain error amplifier forcing sensed Vout to be equal to VREF. It tells that TPS7A1408’s VREF is 0.8V. Following common Equation 1, good starting point for R2 is a 10 kohm based on tradeoff of noise immunity and leakage.

Equation 1. Vout=Vref * (1+R1R2)

With R2 = 10 kohm, yields calculated R1 as 5 kohm.