Alternative ways from original product design could cause unwanted stability issues. In other words, users who apply those changes should take all the possible operating environments into account. Whole operating temperature range and multiple corner cases of product in silicon level should be considered. However, these efforts are only accessible by product designers. The best way for users is to perform a load transient test and observing the amount of ringing on the output in time domain and then measure a Bode plot to see if control loop satisfies stability criteria and wave-forming in frequency domain. Paralleling a capacitor with R1 creates additional one pole and one zero respectively and it’s a basic approach to improve the loop stability by boosting phase lead. And also, it is natural that ac signal on Vout can pass through feed-forward capacitor to the VFB, meaning fast response for control loop from any fluctuation during load transient condition, eventually improving the bandwidth of feedback loop. Figure 2-1 is an open loop small-signal model of NMOS LDO.

Defining small-Signal analysis is out of scope of this application note. In spite of that, users need to understand how C_FF contributes to frequency response. Equation 2 and Equation 3 represent frequency of the zero and pole And they give a hint that this zero (Z_FF) always position at lower frequency than P_FF.

For further details about the LDO stability, see AN-1482 LDO Regulator Stability Using Ceramic Output Capacitors application note. And for further information about using C_FF(feed-forward capacitor), see Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.