Design Goals

Design Description

Modern digital to analog converters (DACs) and analog to digital converters (ADCs) used in high performance test and measurement equipment such as spectrum analyzer, signal generator, waveform generator, wireless communication tester, oscilloscope and data acquisition system, are sensitive to noise in the power supply, as noise can couple into the signal chain, reducing the quality of the measurement. Low-noise power supplies are essential for noise-sensitive ADCs and DACs to maximize signal integrity system performance.

There are two types of power supplies for DC to DC conversion, switching regulators and linear regulators.

Switching regulators are commonly used to step down an input voltage efficiently. However, the output of a switching regulators contains some switching noise that can adversely affect noise sensitive devices. On the other hand, low dropout linear regulators (LDOs) have low output noise, but due to low efficiency, LDOs are only used with low operating headroom to minimize power dissipation.

This application brief goes over the process of creating a high efficiency (> 75%) and ultra low noise (<10 µV_RMS) power supply by combining a switching converter and an LDO. Using switching converter first to efficiently reduce the majority of the input voltage to a lower voltage level that minimizes operating overhead for the LDO. Then the LDO effectively eliminate any remaining noise, providing a low-noise output.

Figure 1 Simplified Schematic

Design Steps

Select LDO

The LDO is selected first for this system, since the LDO must meet or exceed all specifications required by the load.

• VOUT ≥ 3.3 V ±1%
• IOUT ≥ 1 A
• Integrated noise from 10 Hz - 100 kHz < 10 µV_RMS
• PSRR at 100 kHz > 50 dB

LDO in this power supply does not need to meet 12 V system input requirement since a switching regulator is used to step down the input voltage to a voltage closer to output voltage.

Table 2 shows a short list of linear regulators that loosely meet requirements

To create a power supply with the best output noise performance, the LDO with the highest PSRR and lowest noise performance is selected. TPS7A94 has output noise of 0.46 µV_RMS, while also meeting output voltage range, tolerance and current requirements. TPS7A94 has 3.3 µV_RMS less noise compared to the second lowest noise LDO, TPS7A88.

TPS7A96 provides the same low noise performance as TPS7A94 with a higher 2 A output current, which is great for systems that require low noise and more than 1 A current.

TPS7A57, TPS7A91, TPS7A88 are not selected for having lower PSRR than other devices on the list..

TPS7A20 and TPS7A21 do not meet 1 A output current requirement.

Set LDO Output Voltage

Figure 2 shows a simplified regulation circuit, with system output voltage is set by the internal 150 µA current source (I_NR/SS) and the external resistor (R_NR/SS).

To set the LDO output voltage to 3.3 V, calculate the required R_NR/SS resistance with the following equation:

22.1 kΩ is used as it's the closest E96 resistor value available, resulting in a nominal VOUT of 3.315 V.

The 150 µA current source has ±1% tolerance, so a high precision ±0.1% resistor is required to minimize tolerance stack up, and to meet the ±1% output voltage tolerance requirement.

Figure 2 LDO Set VOUT

Select TPS7A94 C_NR/SS

There is a trade-off between output voltage noise and start-up time. The higher the capacitor value, the longer the start-up takes.Table 3 shows the tradeoff between the two.

The goal of the design is to achieve very low noise. While selecting 10 μF for C_NR//SS achieves lowest noise, it also has a long start-up time. Choosing a 4.7 μF capacitor for C_NR/SS only adds 0.04 μVrms of noise, while reducing the start-up time by 15ms. Therefore a single 4.7 μF capacitor is selected to strike a balance between low noise and start-up time.

Evaluate LDO Power Dissipation

R_ϴJA for TPS7A94 is 25.6 °C/W. With 500-mW power dissipation when V_{Or Hr} = 500 mV and I_OUT = 1 A, the resulting temperature increase is only 12.8 °C above ambient.

TPS7A94 EVM Default Setting

Current limit, soft start and UVLO circuits are set to EVM defaults. See TPSM82913 data sheet section 7.3.3 - 7.3.5 for more detail.

Select DC-DC Converter

The DC-DC Converter must meet the following requirements

1. V_IN > 13 V
2. VOUT > 3.8 V
3. IOUT ≥ 1 A

A low noise DC-DC converter reduces overall system noise, especially at frequencies where LDO PSRR is low. Most DC-DC converters do not have output noise specified. TPSM82913 was designed as an LDO replacement with much lower noise than a typical buck converter. With a second-stage filter, TPSM82913 has an integrated noise of 22 µV_RMS from 10 Hz - 100 kHz. For comparison, the integrated noise of a typical switching converter, TPS543620, is 87 µV_RMS.

Set TPSM82913 Output Voltage

To set the output voltage of TPSM82913, feedback resistors R1 and R2 need to be selected.

Figure 4 Feedback Resistors

TPSM82913 has 0.8 V internal reference voltage, and with R2 already set to 4.87 kΩ on the EVM, use the following formula to find R1:

TPSM82913 Input Capacitor Selection

TPSM82913 requires 10 μF minimum input capacitance to be stable. Two 10 μF 25 V X7S ceramic capacitors are used to account for tolerance and capacitance change over temperature and voltage. The EVM also contains a 35 V 47 μF electrolytic capacitor to compensate for the long input power wire's inductance.

TPSM82913 Output Capacitor Selection

Figure 5 Output Capacitor Diagram

TPSM82913 has the following output capacitor requirements when using a second L-C filter: the first L-C filter must have output capacitance between 40 μF and 80 μF, the second stage L-C filter must have at least 20 μF of capacitance, and the total capacitance for both L-C filters must be less than 200 μF. Three 22 μF, 10 V, X7R Ceramic capacitor are used for the 1st stage and 2nd stage to meet the output stability and capacitance requirements.

Set TPSM82913 S-Config

Switching frequency is selected to be 2.2 MHz, to minimize ripple for relatively high VOUT at 3.3 V-4.3 V. Spread spectrum feature is intended to reduce SW frequency noise and higher harmonics. Since NSD noise is measured at much lower frequencies 10 Hz-100 kHz, Spread Spectrum is turned off and since output discharge and synchronization features are also not required, S-Config pin is tired directly to VIN. See Table 7.1 of data sheet for other S-Config pin configurations.

Select Ferrite Bead

A ferrite bead combined with a second set of output capacitors creates a second stage filter that further damps high frequency noise. The ferrite bead needs to have inductance within the design range for stability, a current rating higher than 1 A and low DC resistance.

The TPSM82913 has internal compensation for a ferrite bead with inductance between 10 nH to 50 nH. Ferrite beads are only specified with impedance at 100 MHz, so inductance L can be calculated with equation below and the impedance at 100 MHz is required to be in between 6.3 Ω and 31 Ω.

• Z is the impedance of the ferrite bead at the specified frequency (Typically 100 MHz)
• F is the frequency at which the impedance is measured

The BL18PS080SN1, which has impedance of 8.5Ω at 100 kHz, 4-mΩ DC resistance, 8-A DC rating, and an 0603 package size, meets the desired requirements for this application. Higher impedance ferrite beads, which are also available in larger package sizes, can be selected depending on application requirements.

Total System PSRR

Figure 6 System PSRR

Total system PSRR is the sum of the PSRR of TPSM82913 and TPS7A94. In this case, the PSRR is over 170 dB.

TPSM82913 Thermals

TPSM82913 has, R_ϴJA (junction to ambient resistance) = 25.6 °C/W, at 1 A load, and with 0.5 W power dissipation, resulting temperature increase is only 12.8°C above ambient.

TPSM82913 EN/UVLO

TPSM82913 is enabled when V_IN is raised above V_UVLO of 2.92 V, and since device synchronization is not needed, EN/SYNC pin is directly tied to VIN.

TPSM82913 Current Limit

TPSM82913 has a current limit of 4.3 A, sufficient for 1 A application. If a different current limit is desired for an application, see section 7.3.9 in TPSM82913 data sheet.

Test Results

Figure 7 Noise Density Measurement

Several configurations of TPSM82913 and TPS7A94 are tested inside an enclosed RF chamber, and system output noise is measured with E5052B Spectrum Analyzer. As shown by Noise density graph above, only using a switching converter results in the highest noise, 23 µV_RMS from 10 Hz - 100 kHz.

When the TPS7A94 has less than 360 mV of operating headroom, the system have 13 µV_RMS noise from 10 Hz - 100 kHz.

When TPS7A94 has more than 360 mV of operating headroom, the system have very low noise of 0.5 µV_RMS noise from 10 Hz - 100 kHz.

Noise is lowest when V_{Or Hr} is at least 360 mV, which is 210 mV above the typical drop out voltage of 150 mV. To maintain the same margin when drop out voltage is at the maximum of 240 mV, 450 mV minimum operating headroom is required.

In conclusion, a low noise DC-DC switching regulator used in conjunction with ultra-low noise LDO TPS7A94 with sufficiently high head room, can achieve ultra-low noise performance and high efficiency.