SBVS037Q August   2003  – September 2024 TPS732

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Dropout Voltage
      5. 6.3.5 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation With 1.7V ≤ VIN ≤ 5.5V and VEN ≥ 1.7V
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
          1. 7.4.1.1.1 Power Dissipation
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.3 Enable Pin and Shutdown

The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5V (maximum) turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shut down the regulator, all charge is removed from the pass transistor gate. A VEN above 1.7V (minimum) turns the regulator on and the output ramps back up to a regulated VOUT (see Figure 5-39).

When shutdown capability is not required, connect EN to VIN. However, the pass transistor potentially does not discharge using this configuration, causing the pass transistor to be left on (enhanced) for a significant time after VIN is removed. This scenario results in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power up. In addition, for VIN ramp times slower than a few milliseconds, the output potentially overshoots upon power up.

Current limit foldback prevents device start-up under some conditions. See the Internal Current Limit section.