SBVS037Q August   2003  – September 2024 TPS732

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Dropout Voltage
      5. 6.3.5 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation With 1.7V ≤ VIN ≤ 5.5V and VEN ≥ 1.7V
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
          1. 7.4.1.1.1 Power Dissipation
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.1 Output Noise

A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS732 and generates approximately 32µVRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

Equation 1. TPS732

Because the value of VREF is 1.2V, this relationship reduces to:

Equation 2. TPS732

An internal 27kΩ resistor in series with the noise-reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise-reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship:

Equation 3. TPS732

for CNR = 10nF.

This noise-reduction effect is shown as RMS Noise Voltage vs CNR (Figure 5-33) in the Typical Characteristics section.

The TPS73201 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient performance.

The TPS732 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass transistor above VOUT. The charge pump generates approximately 250μV of switching noise at approximately 4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT.