SBVS074N January   2007  – June 2024 TPS74801

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50 mA
    7. 5.7 Typical Characteristics: IOUT = 1 A
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable/Shutdown
      2. 6.3.2 Power Good
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjusting the Output Voltage
      2. 7.1.2 Input, Output, and Bias Capacitor Requirements
      3. 7.1.3 Transient Response
      4. 7.1.4 Dropout Voltage
      5. 7.1.5 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
        1. 8.1.2.1 Evaluation Modules
        2. 8.1.2.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal reference (Adj.) TA = 25°C 0.796 0.8 0.804 V
VOUT Output voltage range VIN = 5 V, IOUT = 1.5 A VREF 3.6 V
Accuracy(1) 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A (Legacy Chip) –2 ±0.5 2 %
2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A (New Chip) –1 ±0.3 1
ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (Legacy Chip) 0.03 %/V
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (New Chip) 0.001
ΔVOUT(ΔIOUT) Load regulation 50 mA ≤ IOUT ≤ 1.5 A 0.09 %/A
VDO VIN dropout voltage(2) IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (Legacy Chip) (3) 60 165 mV
IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (New Chip) (3) 50 100
VBIAS dropout voltage(2) IOUT = 1.5 A, VIN = VBIAS (Legacy Cip) 1.31 1.6 V
IOUT = 1.5 A, VIN = VBIAS (New Chip) 1.31 1.43
ICL Output current limit VOUT = 80% × VOUT(nom) 2 5.5 A
IBIAS BIAS pin current (Legacy Chip) 1 2 mA
(New Chip)  1 1.2
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V (Legacy Chip) 1 50 µA
VEN ≤ 0.4 V (New Chip)  0.85 2.75
IFB Feedback pin current (Legacy Chip) –1 0.15 1 µA
(New Chip) –30 0.15 30 nA
PSRR Power-supply rejection (VIN to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 60 dB
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 30
Power-supply rejection (VBIAS to VOUT) 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 50
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 59
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) 30
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) 50
Vn Output noise voltage BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF (Legacy Chip) 25 × VOUT μVrms
BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF (New Chip) 20 × VOUT
tSTR Minimum startup time RLOAD for IOUT = 1.0 A, CSS = open (Legacy Chip) 200 µs
RLOAD for IOUT = 1.0 A, CSS = open (New Chip) 250
ISS Soft-start charging current VSS = 0.4 V (Legacy Chip) 440 nA
VSS = 0.4 V (New Chip) 530
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis (Legacy Chip) 50 mV
(New Chip) 55
VEN(dg) Enable pin deglitch time 20 µs
IEN Enable pin current VEN = 5 V (Legacy Chip)  0.1 1 µA
VEN = 5 V (New Chip) 0.1 0.3
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT (Legacy Chip) 0.3 V
IPG = 1 mA (sinking), VOUT < VIT (New Chip) 0.125
IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT (Legacy Chip) 0.1 1 µA
VPG = 5.25 V, VOUT > VIT (New Chip) 0.001 0.05
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 ℃
Reset, temperature decreasing 140
RPULLDOWN Output pulldown resitance VBIAS = 5V, VEN = 0V 0.83 1 kΩ
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 5-11.