SBVS082K June   2007  – June 2024 TPS74901

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics: IOUT = 50mA
    7. 5.7 Typical Characteristics: IOUT = 1 A
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Shutdown
      2. 6.3.2 Power-Good
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and BIAS Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
      5. 7.1.5 Programmable Soft-Start
      6. 7.1.6 Sequencing Requirements
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
        2. 7.4.1.2 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
        1. 8.1.2.1 Evaluation Modules
        2. 8.1.2.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TPS74901 RGW Package,20-Pin VQFN(Top View)Figure 4-1 RGW Package,20-Pin VQFN(Top View)
TPS74901 DRC Package,10-Pin VSON With Thermal Pad(Top View)Figure 4-3 DRC Package,10-Pin VSON With Thermal Pad(Top View)
TPS74901 KTW Package (Legacy Chip),7-Pin DDPAK/TO-263(Top View)Figure 4-2 KTW Package (Legacy Chip),7-Pin DDPAK/TO-263(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME DDPAK/TO-263 VQFN VSON
BIAS 6 10 4 I Bias input voltage for error amplifier, reference, and internal control circuits.
EN 7 11 5 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating.
FB 2 16 8 I This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
GND 4 12 6 — Ground
IN 5 5, 6, 7, 8 1, 2 I Unregulated input to the device.
NC — 2, 3, 4, 13, 14, 17 — — No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
OUT 3 1, 18, 19, 20 9, 10 O Regulated output voltage. A small capacitor (total typical capacitance
≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability.
PG — 9 3 O Power-good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pullup resistor from 10kΩ to 1MΩ must be connected from this pin to a supply up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary.
SS 1 15 7 — Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 100µs.
Thermal Pad — Solder to the ground plane for increased thermal performance.