SBVS179B December   2011  – August 2015 TPS7A8101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Start-Up
      4. 7.3.4 Undervoltage Lock-Out (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Component Values
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Dropout Voltage
        2. 8.2.1.2 Minimum Load
        3. 8.2.1.3 Input and Output Capacitor Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Noise
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
    4. 10.4 Power Dissipation
    5. 10.5 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10 Layout

10.1 Layout Guidelines

10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device.

10.2 Layout Example

TPS7A8101 layout_slvsck0.gifFigure 33. TPS7A8101 Layout Example

10.3 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A8101 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A8101 into thermal shutdown degrades device reliability.

10.4 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 3:

Equation 3. TPS7A8101 q_pd_bvs064.gif

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed-circuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 4:

Equation 4. TPS7A8101 q_max_therm_resist.gif

Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 34.

TPS7A8101 ai_theta_ja_bvs135.gif

NOTE:

θJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 34. θJA vs Board Size

Figure 34 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.

NOTE

When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the section.

10.5 Estimating Junction Temperature

Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 5). For backwards compatibility, an older θJC,Top parameter is listed as well.

Equation 5. TPS7A8101 q_new_metrics_bvs066.gif

Where PD is the power dissipation shown by Equation 4, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (as Figure 35 shows).

TPS7A8101 ai_measuring_point_bvs135.gifFigure 35. Measuring Points for TT and TB

NOTE

Both TT and TB can be measured on actual application boards using an infrared thermometer.

For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com.

By looking at Figure 36, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 5 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size.

TPS7A8101 ai_psi_jt_jb_bvs135.gifFigure 36. ΨJT and ΨJB vs Board Size

For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website.