The TPS7A39 device is a dual, monolithic, high-PSRR, positive and negative low-dropout (LDO) voltage regulator capable of sourcing (and sinking) up to 150 mA of current. The regulated outputs can be independently and externally adjusted to symmetrical or asymmetrical voltages, making this device an ideal dual, bipolar power supply for signal conditioning.
Both positive and negative outputs of the TPS7A39 ratiometrically track each other during startup to mitigate floating conditions and other power-supply sequencing issues common in dual-rail systems. The negative output can regulate up to 0 V, extending the common-mode range for single-supply amplifiers. The TPS7A39 also features high PSRR to eliminate power-supply noise, such as switching noise, that can compromise signal integrity.
Both regulators are controlled with a single positive logic enable pin for interfacing with standard digital logic. A capacitor-programmable soft-start function controls in-rush current and start-up time. The internal reference voltage of the TPS7A39 can be overridden with an external reference to enable precision outputs, output voltage margining, or to track other power supplies. Additionally, the TPS7A39 has a buffered reference output that can be used as a voltage reference for other components in the system.
These features make the TPS7A39 a robust, simplified solution to power operational amplifiers, digital-to-analog converters (DACs), and other precision analog circuitry.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A39 | WSON (10) | 3.00 mm × 3.00 mm |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | INP | I | Positive input. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section for more information. |
2 | EN | I | Enable pin. Driving this pin to logic high (VEN ≥ VIH(EN)) enables the device; driving this pin to logic low (VEN ≤ VIL(EN)) disables the device. If enable functionality is not required, this pin must be connected to INP; see the Application and Implementation section for more detail. The enable voltage cannot exceed the input voltage (VEN ≤ VINP). |
3 | NR/SS | — | Noise-reduction, soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and enables soft-start and start-up tracking. A 10-nF or larger capacitor (CNR/SS) is recommended to be connected from NR/SS to GND to maximize or optimize ac performance and to ensure start-up tracking. This pin can also be driven externally to provide greater output voltage accuracy and lower noise, see the User-Settable Buffered Reference section for more information. |
4 | GND | — | Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance connection. |
5 | INN | I | Negative input. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section for more information. |
6 | OUTN | O | Negative output. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the output capacitor as close to the output as possible; see the Capacitor Recommendations section for more information. |
7 | FBN | I | Negative output feedback pin. This pin is used to set the negative output voltage. Although not required, a 10-nF feed-forward capacitor from FBN to OUTN (as close to the device as possible) is recommended to maximize ac performance. Nominally this pin is regulated to VFBN. Do not connect to ground. |
8 | BUF | O | Buffered reference output. This pin is connected to FBN through R2 and the voltage at this node is inverted and scaled up by the negative feedback network to provide the desired output voltage. The buffered reference can be used to drive external circuits, and has a 1-mA maximum load. |
9 | FBP | I | Positive output feedback pin. This pin is used to set the positive output voltage. Although not required, a 10-nF feed-forward capacitor from FBP to OUTP (as close to the device as possible) is recommended to maximize ac performance. Nominally this pin is regulated to VFBP. Do not connect this pin directly to ground. |
10 | OUTP | O | Positive output. A 10-μF(1) or larger capacitor must be tied from this pin to ground to ensure stability. Place the output capacitor as close to the output as possible; see the Capacitor Recommendations section for more information. |
Pad | Thermal Pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | INP | –0.3 | 36 | V |
INN | –36 | 0.3 | ||
OUTP | –0.3 | VINP + 0.3(5) | ||
OUTN | VINN – 0.3(4) | 0.3 | ||
FBP | –0.3 | VINP + 0.3(7) | ||
BUF | –1 | VINP + 0.3(7) | ||
NR/SS | –0.3 | VINP + 0.3(8) | ||
FBN | VINN – 0.3(3) | 0.3 | ||
EN | –0.3 | VINP + 0.3(6) | ||
Current | Output current | Internally limited | ||
Buffer current | 2 | mA | ||
Temperature | Operating junction temperature, TJ | –55 | 150 | °C |
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
|VINx| | Supply voltage magnitude for either regulator | 3.3 | 33 | V | |
VEN | Enable supply voltage | 0 | VINP | V | |
VOUTP | Positive regulated output voltage range | VFBP | 30 | V | |
VOUTN | Negative regulated output voltage range | –30 | VFBN | V | |
IOUTx | Output current for either regulator | 0.005(2) | 150 | mA | |
IBUF | Output current from the BUF pin | 0 | 120 | 1000 | µA |
CINx | Input capacitor for either regulator | 4.7 | 10(1) | µF | |
COUTx | Output capacitor for either regulator | 4.7 | 10(1) | µF | |
CNR/SS | Noise-reduction and soft-start capacitor | 0(3) | 10 | 1000 | nF |
CFFP | Positive channel feed-forward capacitor; connect from VOUTP to FBP | 0 | 10 | 100 | nF |
CFFN | Negative channel feed-forward capacitor; connect from VOUTN to FBN | 0 | 10 | 100 | nF |
R2P | Lower positive feedback resistor | 10 | 240 | kΩ | |
R2N | Lower negative feedback resistor (from FBN to BUF) | 10 | 240 | kΩ | |
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS7A39 | UNIT | |
---|---|---|---|
DSC (WSON) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 44.4 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 33.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 19.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 19.5 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | 2.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VINP | Input voltage range, positive channel | 3.3 | 33 | V | |||
VINN | Input voltage range, negative channel | –33 | –3.3 | V | |||
VUVLOP(rising) | Undervoltage lockout threshold, positive channel |
VINP rising, VINN = –3.3 V | 1.4 | 3.1 | V | ||
VUVLOP(hys) | Undervoltage lockout threshold, positive channel hysteresis | VINP falling, VINN = –3.3 V | 120 | mV | |||
VUVLON(falling) | Undervoltage lockout threshold, negative channel |
VINN falling, VINP = 3.3 V | –3.1 | –1.4 | V | ||
VUVLON(hys) | Undervoltage lockout threshold, negative channel, hysteresis | VINN rising, VINP = 3.3 V | 70 | mV | |||
VNR/SS | Internal reference voltage | 1.172 | 1.19 | 1.208 | V | ||
VFBP | Positive feedback voltage | 1.170 | 1.188 | 1.206 | V | ||
VFBN | Negative feedback voltage | –10 | 3.7 | 10 | mV | ||
VOUT | Output voltage range(2) | Positive channel | VFBP | 30 | V | ||
Negative channel | –30 | VFBN(1) | |||||
VOUTP accuracy | VINP(nom) ≤ VINP ≤ 33 V, 1 mA ≤ IOUTP ≤ 150 mA, 1.2 V ≤ VOUTP(nom) ≤ 30 V |
–1.5 | 1.5 | %VOUT | |||
VOUTN accuracy(3) | –33 V ≤ VINN ≤ VINN(nom), –150 mA ≤ IOUTN ≤ –1 mA, –30 V ≤ VOUTN(nom) ≤ –1.2 V | –3 | 3 | %VOUT | |||
Negative VOUT channel accuracy | –33 V ≤ VINN ≤ VINN(nom) , –150 mA ≤ IOUTN ≤ 1 mA, –1.2 V < VOUTN(nom) < 0 V | –36 | 36 | mV | |||
–33 V ≤ VINN ≤ VINN(nom) , –150 mA ≤ IOUTN ≤ 1 mA, VOUTN(nom) = 0 V | –12 | 12 | |||||
ΔVOUT(ΔVIN) / VOUT(NOM) | Line regulation, positive channel | VINP(nom) ≤ VINP ≤ 33 V | 0.035 | %VOUT | |||
Line regulation, negative channel | –33 V ≤ VINN ≤ VOUT(nom) + 1 V | 0.125 | |||||
ΔVOUT(ΔIOUT) / VOUT(NOM) | Load regulation, positive channel | 1 mA ≤ IOUTP ≤ 150 mA | –0.09 | %VOUT | |||
Load regulation, negative channel | –150 mA ≤ IOUTN ≤ –1 mA | 0.715 | |||||
VDO | Dropout voltage | Positive channel | IOUTP = 50 mA, 3.3 V ≤ VINP(nom) ≤ 33.0 V, VFBP = 1.070 V |
175 | 300 | mV | |
IOUTP = 150 mA, 3.3 V ≤ VINP(nom) ≤ 33.0 V, VFBP = 1.070 V |
300 | 500 | |||||
Negative channel | IOUTN = –50 mA, –3.3 V ≤ VINN(nom) ≤ –33.0 V, VFBN = 0.0695 V |
–250 | –145 | ||||
IOUTN = –150 mA, –3.3 V ≤ VINN(nom) ≤ –33.0 V, VFBN = 0.0695 V |
–400 | –275 | |||||
VBUF | Buffered reference output voltage | VNR/SS | V | ||||
VBUF/IBUF | Buffered reference load regulation | IBUF = 100 µA to 1 mA | 1 | mV/mA | |||
VBUF – VNR/SS | Output buffer offset voltage | VNR/SS = 0.25 V to 1.2 V | –4 | 3 | 8 | mV | |
VOUTP–VOUTN | DC output voltage difference with a forced REF voltage | VNR/SS = 0.25 V to 1.2 V | –10 | 10 | %VNR/SS | ||
ILIM | Current limit | Positive channel | VOUTP = 90% VOUTP(nom) | 200 | 330 | 500 | mA |
Negative channel | VOUTN = 90% VOUTN(nom) | –500 | –300 | –200 | |||
ISUPPLY | Supply current | Positive channel | IOUTP = 0 mA, R2N = open, VINP = 33 V | 75 | 150 | µA | |
IOUTP = 150 mA, R2N = open, VINP = 33 V | 904 | ||||||
Negative channel | IOUTN = 0 mA, VOUTN(nom)= 0 V, R2N = open, VINN = –33 V | –150 | –60 | ||||
IOUTN = 150 mA, R2N = open, VINN = –33 V | –1053 | ||||||
ISHDN | Shutdown supply current | Positive channel | VEN = 0.4 V, VINP = 33 V | 3.75 | 6.5 | µA | |
Negative channel | VEN = 0.4 V, VINN = –33 V | –4.5 | –2.25 | ||||
IFBx | Feedback pin leakage current | Positive channel | 5.5 | 100 | nA | ||
Negative channel | –100 | –9.7 | |||||
INR/SS | Soft-start charging current | VNR/SS = 0.9 V | 3 | 5.1 | 6.7 | µA | |
IEN | Enable pin leakage current | VEN = VINP = 33 V | 0.02 | 1 | µA | ||
VIH(EN) | Enable high-level voltage | 2.2 | VINP | V | |||
VIL(EN) | Enable low-level voltage | 0 | 0.4 | V | |||
PSRR | Power-supply rejection ratio | |VIN| = 6 V, |VOUT(nom)| = 5 V, COUT = 10 μF, CNR/SS = CFF= 10 nF, f = 120 Hz | 69 | dB | |||
Vn | Output noise voltage | Positive channel | VINP = 3.3 V, VOUTP(nom) = VNR/SS, COUTP = 10 μF, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz | 20.63 | µVRMS | ||
VINP = 6 V, VOUTP(nom) = 5 V, COUTP = 10 μF, CNR/SS = CFF = 10 nF, BW = 10 Hz to 100 kHz | 26.86 | ||||||
Negative channel | VINN = –3 V, VOUTN(nom) = –VNR/SS, COUTP = 10 μF, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz | 22.13 | |||||
VINN = –6 V, VOUTN(nom) = –5 V, COUTP = 10 μF, CNR/SS = CFF= 10 nF, BW = 10 Hz to 100 kHz | 28.68 | ||||||
RNR/SS | Filter resistor from band gap to NR pin | 350 | kΩ | ||||
Tsd | Thermal shutdown temperature | Shutdown, temperature increasing | 175 | °C | |||
Reset, temperature decreasing | 160 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tEN(delay) | Delay time from EN low-to-high transition to 2.5% VOUTP | From EN low-to-high transition to VOUTP = 2.5% × VOUTP(nom) | 300 | µs | ||
tstart-up | Delay time from EN low-to-high transition to both outputs reaching 95% of final value | From EN low-to-high transition to VOUTP = VOUTP(nom) × 95% and VOUTN = VOUTN(nom) × 95% | 1.1 | ms | ||
tPstart-Nstart | Delay time from VOUTP leaving a high-impedance state to VOUTN leaving a high-impedance state | From VOUTP = VOUTP(nom) × 2.5% to VOUTN = VOUTN(nom) × 2.5% | –40 | –17 | 40 | µs |
Δ|VOUTP – VOUTN| | Voltage difference between the positive and negative output | During tPstart-Nstart | 75 | 300 | mV |
NOTE:
Slow ramps (trise(VINx) > 10 ms typically) on VINx with EN tied to VINP does not meet the tracking specification. Use a resistor divider from VINP to EN for these applications.VOUTP = 5 V, IOUTP = 150 mA, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = 10 nF |
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CFFx = 10 nF |
IOUTP = 150 mA, VINP = VEN, VOUTN = –VOUTP, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CFFx = 10 nF |
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = 10 nF |
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = –VOUTN = 5 V, VINP = –VINN = 12 V |
VINP = 5.5 V to 10 V at 1 V/µs, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA, IOUTP = 150 mA |
VINP = 5.5 V to 10 V at 4 V/µs, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA, IOUTP = 150 mA |
VINP = 6 V, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA, IOUTP = 1 mA to 150 mA at 1 A/µs |
VOUTN = 0 V |
VOUTN = –1.19 V |
VOUTN = –24 V |
VOUTN = –15 V, VINN = –16 V |
VOUTP = 1.188 V, VINP = 3.3 V |
VOUTP = 30 V, VINP = 33 V |
VOUTP = 15 V |
VOUTP = 1.188 V |
VINP = 3.3 V |
VOUTP = 1.188 V |
VOUTN = –1.19 V |
VOUTP = 5 V, IOUTP = 0 mA, VOUTN = –5 V, IOUTN = 150 mA, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V, CNR/SS = CFFx = 10 nF |
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V, CNR/SS = CFFx = 10 nF, COUTP = 10 µF |
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V, CNR/SS = CFFP = 10 nF |
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V, CFFx = 10 nF |
IOUTN = –150 mA, VINP = VEN, VOUTN = –VOUTP, IOUTP = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CFFx = 10 nF |
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CNR/SS = 10 nF |
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTN = –5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CNR/SS = CFFx = 10 nF |
VOUTP = –VOUTN = 5 V, VINP = –VINN = 15 V |
VINN = –5.5 V to –10 V at 1 V/µs, VOUTP = –VOUTN = 5 V, IOUTN = –150 mA, IOUTP = 0 mA |
VINN = –5.5 V to –10 V at 4 V/µs, VOUTP = –VOUTN = 5 V, IOUTN = –150 mA, IOUTP = 0 mA |
VINN = –6 V, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA, IOUTN = –1 mA to –150 mA at 1 A/µs |
VOUTN = 0 V, VINN = –3.3 V |
VOUTN = –15 V |
VOUTN = –1.2 V, VINN = –3.3 V |
VOUTN = –30 V, VINN = –33 V |
VOUTP = 15 V, VINP = 16 V |
VOUTP = 1.188 V |
VOUTP = 24 V |
VOUTN = –1.19 V |
VOUTN = –3.3 V |
VOUTN = –1.19 V |
The TPS7A39 is an innovative linear regulator (LDO) targeted at powering the signal chain, capable of up to ±33 V on the inputs and regulating up to ±30 V on the outputs at up to 150 mA of load current. The device uses an LDO topology that, by design, delivers ratiometric start-up tracking in most applications. The TPS7A39 has several other features, as listed in Table 1, that simplify using the device in a variety of applications.
NOTE
Throughout this document, x is used to designate that the condition or component applies to both the positive and negative regulators (for example, CFFx means CFFP and CFFN).
VOLTAGE REGULATION | SYSTEM START-UP | INTERNAL PROTECTION |
---|---|---|
Reference input/output | Ratiometric start-up tracking | Current limit |
High-PSRR output | Programmable soft-start | Thermal shutdown |
Fast transient response | Sequencing controls |
An LDO functions as a buffered op-amp in which the input signal is the internal reference voltage (VNR/SS), as shown in Figure 59, and in normal regulation VFBP = VNR/SS. Sharing a single reference ensures that both channels track each other during start-up.
VNR/SS is designed to have a very low-bandwidth at the input to the error amplifier through the use of a low-pass filter. As such, the reference can be considered as a pure dc input signal.
As Figure 60 shows, the negative LDO on the device regulates with a VFBN = 0 V and inverts the positive reference (VBUF). This topology allows the negative regulator to regulate down to 0 V.
Each LDO responds quickly to a transient on the input supply (line transient) or the output current (load transient). This LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac and large-signal conditions.
The performance and internal layout of the device minimizes the coupling of noise from one channel to the other channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.
The noise-reduction and soft-start capacitor (CNR/SS) and feed-forward capacitor (CFFx) easily reduce the device noise floor and improve PSRR; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.
As Figure 61 shows, the device internally generated band-gap voltage outputs at the NR/SS pin. An internal resistor (RNR) and an external capacitor (CNR/SS) control the rise time of the voltage at the VNR/SS pin, setting the soft-start time. This network also filters out noise from the band gap, reducing the overall noise floor of the device.
Driving the NR/SS pin with an external source can improve the device accuracy and can reduce the device noise floor, along with enabling the device to regulate the positive channel to voltages below the device internal reference.
NOTE:
* denotes external components.When either EN or UVLOx are low, the device connects a resistance from VOUTx to GND, discharging the output capacitance. The active discharge circuit requires |VOUTx| ≥ 0.6 V (typ) to discharge the output because the NPN pulldown has a minimum VCE requirement.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops below the targeted output voltage. The TPS7A39 is a bipolar device, and as such, reverse voltage conditions (|VOUTx| ≥ |VINX| + 0.3 V) can breakdown the emitter to base diode and also cause a breakdown of the parasitic bipolar formed in the substrate; see the Reverse Current section for more details.
When either EN or UVLOx are low, the device outputs a small amount of leakage current. The leakage current is typically handled by the maximum R2x resistor value of 240 kΩ. However, if the device is placed in unity gain (no R2x resistor) this leakage current causes the output to slowly rise until the discharge circuit (as shown in Figure 62) has enough headroom to clamp the output voltage (typically ±0.6 V).
In many different applications, the power-supply output must turn-on within a specific window of time because of sequencing requirements, ensuring proper operation of the load, or to minimize the loading on the input supply.
Both LDOs start-up are well-controlled and user-adjustable through the CNR/SS capacitor, solving the demanding requirements faced by many power-supply design engineers in a simple fashion. For start-up tracking to work correctly. a minimum 4.7-nF CNR/SS capacitor is required. For more information on startup tracking, see the Noise-Reduction and Soft-Start Capacitor (CNR/SS) section.
Figure 63 shows how both regulators use a common reference, which enables start-up tracking. Using the same reference voltage for both the positive and negative regulators ensures that the regulators start-up together in a controlled fashion; see Figure 24 and Figure 25.
Ramps on VINx with EN = VINP that are slower than the soft-start time do not have start-up tracking. If ramps slower than the soft-start time are used then enable should be used to start the device to ensure start-up tracking. A small mismatch between the positive and negative internal enable thresholds means that one channel turns on at a slightly lower input voltage than the other channel. This mismatch is typically not a problem in most applications and is easily solved by controlling the start-up with enable. The external signal can come from the input power supply power-good indicator, a voltage supervisor output such as the TPS3701, or from another source.
Figure 64 and Table 2 describe how the turn-on and turn-off times of both LDOs (respectively) is controlled by setting the enable circuit (EN) and undervoltage lockout circuit (UVLOP and UVLON).
POSITIVE INPUT VOLTAGE (VINP) | NEGATIVE INPUT VOLTAGE (VINN) | ENABLE STATUS | LDO STATUS | ACTIVE DISCHARGE |
---|---|---|---|---|
VINP ≥ VUVLOP | VINN ≤ VUVLON | EN = 1 | On | Off |
EN = 0 | Off | On(1) | ||
VINP ≥ VUVLOP | VINN > VUVLON | EN = don't care | Off | On(1) |
VINP < VUVLOP | VINN ≤ VUVLON | EN = don't care | Off | On(1) |
VINP < VUVLOP – VHYSP | VINN > VUVLON – VHYSN | EN = don't care | Off | On(1) |
The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN ≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. In applications that do not use the enable control, connect EN to VINP.
A slow VINx ramp directly connecting EN to VINP can cause the start-up tracking to move out of specification. Under slow ramp conditions, use a resistor divider from VINP to ensure start-up tracking.
The UVLO circuit responds quickly to glitches on the input supplies and attempts to disable the output of the device if either of these rails collapse.
As a result of the fast response time of the input supply UVLO circuit, fast and short line transients well below the input supply UVLO falling threshold (brownouts) can cause momentary glitches during the edges of the transient. These glitches are typical in most LDOs. The local input capacitance prevents severe brown-outs in most applications; see the Undervoltage Lockout (UVLOx) Control section for more details. Fast line transients can cause the outputs to momentarily shut off, and can be mitigated through using the recommended 10-µF input capacitor. If this becomes a problem in the system, increasing the input capacitance prevents these glitches from occurring.
The device regulates to the nominal output voltage under the following conditions:
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device (as a bipolar junction transistor, or BJT) is in saturation and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations.
The device is disabled under the following conditions:
Table 3 shows the conditions that lead to the different modes of operation.
OPERATING MODE | PARAMETER | |||
---|---|---|---|---|
VIN | VEN | IOUT | TJ | |
Normal mode | |VINx| > |VOUT(nom)| + |VDOx| and |VINx| > |VINx(min)| |
VEN > VIH | |IOUTx| < |ILIMx| | T J < 125°C |
Dropout mode | |VINx(min)| < |VINx| < |VOUTx(nom)| + |VDOx| | VEN > VIH | — | TJ < 125°C |
Disabled mode (any true condition disables the device) |
— | VEN < VIL | — | TJ > TSD |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Successfully implementing an LDO in an application depends on the application requirements. This section discusses key device features and how to best implement the LDO to achieve a reliable design.
Figure 65 shows that each LDO resistor feedback network sets its output voltage. The positive LDO output voltage range is VNR/SS to 30 V and the negative LDO output voltage range is 0 V to –30 V.
Equation 1 relates the values of R1P and R2P to VOUTP(NOM) and VNR/SS to set the positive output voltage. Equation 2 relates the values of R1N and R2N to VOUTN(NOM) and VNR/SS to set the negative output voltage.
The positive LDO is configured as a noninverting op amp, whereas the negative LDO is an inverting op amp.
Substituting VNR/SS with VFBP on the positive channel and VNR/SS with VBUF on the negative channel gives a more accurate relationship.
Equation 3 and Equation 2 are rearranged versions of Equation 1 and Equation 2, with the above substitutions made.
The minimum bias current through both feedback networks is 5 µA to ensure accuracy.
For even tighter accuracy, take into account the input bias current into the error amplifiers (IFBP and IFBN) and use 0.1% resistors. Overriding the internal reference with a high accuracy external reference can also improve the accuracy of the device.
Table 4 and Table 5 show the resistor combinations for several common output voltages using commercially available, 1% tolerance resistors.
TARGETED OUTPUT VOLTAGE (V) | FEEDBACK RESISTOR VALUES(1) | CALCULATED OUTPUT VOLTAGE (V) | |
---|---|---|---|
R1P (kΩ) | R2P (kΩ) | ||
1.5 | 2.67 | 10.0 | 1.50 |
1.8 | 5.23 | 10.0 | 1.80 |
2.5 | 11.0 | 10.0 | 2.49 |
3.0 | 15.4 | 10.0 | 3.00 |
3.3 | 17.8 | 10.0 | 3.29 |
5.0 | 32.4 | 10.0 | 5.02 |
9.0 | 66.5 | 10.0 | 9.07 |
12.0 | 90.9 | 10.0 | 12.0 |
15.0 | 115 | 10.0 | 14.8 |
24.0 | 191 | 10.0 | 23.8 |
30.0 | 243 | 10.0 | 29.8 |
TARGETED OUTPUT VOLTAGE (V) | FEEDBACK RESISTOR VALUES(1) | CALCULATED OUTPUT VOLTAGE (V) | |
---|---|---|---|
R1N (kΩ) | R2N (kΩ) | ||
-0.3 | 2.55 | 10.0 | -0.303 |
-1.5 | 12.7 | 10.0 | -1.51 |
-1.8 | 15.0 | 10.0 | -1.78 |
-2.5 | 21.0 | 10.0 | -2.49 |
-3.0 | 25.5 | 10.0 | -3.03 |
-3.3 | 28.0 | 10.0 | -3.33 |
-5.0 | 42.2 | 10.0 | -5.04 |
-9.0 | 75.0 | 10.0 | -8.91 |
-12.0 | 100 | 10.0 | -11.9 |
-15.0 | 127 | 10.0 | -15.1 |
-24.0 | 200 | 10.0 | -23.8 |
-30.0 | 255 | 10.0 | -30.3 |
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output pins. The device is also designed to be stable with aluminum polymer and tantalum polymer capacitors with ESR < 75 mΩ.
Electrolytic capacitors (along with higher ESR polymer capacitors) can also be used if capacitors (meeting the minimum capacitance and ESR requirements ) are used in parallel.
Take the effective ESR for stability when the impedance of the capacitor is at its minimum. At the minimum level, the capacitance and parasitic inductance cancel each other and provides the DC ESR.
Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for an effective capacitance derating of approximately 50%, but at higher VIN and VOUT conditions (that is, VIN = 5.5 V to VOUT = 5.0 V) the derating can be greater than 50% and must be taken into consideration.
For high performance applications polymer capacitors are ideal as they do not experience the large deratings of ceramic capacitors.
The device is designed and characterized for operation with ceramic capacitors of 10 µF or greater (2.2 µF or greater of effective capacitance) at each input and output.
Locate the input and output capacitors as near as practical to the respective input and output pins to minimize the trace inductance from the capacitor to the device. If the LDO is used to produce low output voltages (below 5 V), a 4.7-µF output capacitor can be used. If a 4.7-µF output capacitor is used, be sure to account for the derating of the capacitors during design.
Large, fast line transients on the input supplies can cause the device output to momentarily turn off. Typically these transients do not occur in most applications, but when these transients do occur use a larger input capacitor to slow down the line transient. If the system has input line transients that are faster than 0.5 V/µs, increase the input capacitance.
Although a feed-forward capacitor (CFFx) from the FBx pin to the OUTx pin is not required to achieve stability, a 10-nF external CFFx capacitor optimizes the transient, noise, and PSRR performance. The maximum recommended value for CFFx is 100 nF.
A larger CFFx can dominate the start-up time set by CNR/SS, for more information see the Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report.
Although a noise-reduction and soft-start capacitor (CNR/SS) from the NR/SS pin to GND is not required, CNR/SS is highly recommended to control the start-up time and reduce the noise-floor of the device. For start-up tracking to function correctly, a minimum 4.7-nF capacitor is required. As the time constant formed by the feedback resistors and feed-forward capacitors increases, the value of the CNR/SS capacitor must also be increased for startup tracking to work correctly. To figure out how to calculate the time constant of the feedback network see the Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report.
The voltage at the NR/SS pin, whether driven internally or externally, is buffered with a high-bandwidth, low-noise op amp. The BUF pin can be used as a voltage reference in many signal chain applications.
The internal reference of the LDO can be overridden using an external source to increase the accuracy of the LDO and lower the output noise. To override the internal reference connect the external source to the NR/SS pin of the LDO. In order to overdrive the internal reference the external source must be able to source or sink 100 µA or greater.
The internal reference achieves a 2% accuracy from –40°C to +125°C; using an external reference can help achieve better accuracy over temperature.
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CNR/SS). This soft-start eliminates power-up initialization problems.
The output voltage (VOUTx) rises proportionally to VNR/SS during start-up. As such, the time required for VNR/SS to reach its nominal value determines the rise time of VOUTx (start-up time).
The soft-start ramp time depends on the soft-start charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Equation 5 calculates the approximate soft-start ramp time (tSS):
Values for the soft-start charging currents, RNR/SS, and the device internal CNR/SS are provided in the table.
In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, the in-rush current can be estimated by Equation 6:
where
The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum operational voltage range, and ensures that the device properly shuts down when the input supply collapses.
Figure 66 and Table 6 explain the UVLOx circuit response to various input voltage events, assuming VEN ≥ VIH(EN).
The positive and negative UVLO circuits are internally ANDed together. As such, if either supply collapses, both outputs turn-off and VNR/SS is pulled low internally.
REGION | EVENT | VOUTx STATUS | COMMENT |
---|---|---|---|
A | Turn-on, |VINx| ≤ |VUVLOx| | 0 | Start-up |
B | Regulation | 1 | Regulates to target VOUTx |
C | Brownout,|VINx| ≥ |VUVLOx – VHYSx| | 1 | The output can fall out of regulation but the device is still enabled |
D | Regulation | 1 | Regulates to target VOUTx |
E | Brownout, |VINx| < |VUVLOx – VHYSx| | 0 | The device is disabled and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLOx rising threshold is reached by the input voltage and a normal start-up then follows. |
F | Regulation | 1 | Regulates to target VOUTx |
G | Turn-off, |VINx| < |VUVLOx – VHYSx| | 0 | The output falls because of the load and active discharge circuit |
Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time; however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall time of the input supply when operating near the minimum VINx.
LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The output noise is primarily a result of the band-gap reference and error amplifier noise.
PSRR is a measure of how well the LDO control-loop rejects signals from VINx to VOUTx across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 7 gives the PSRR calculation as a function of frequency for the input signal [VINx(f)] and output signal [VOUTx(f)].
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.
Figure 67 shows a simplified diagram of PSRR versus frequency.
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to sensitive system components.
Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting the other output. This attenuation appears in load transient tests on the other output; however, to numerically quantify the rejection, the output channel isolation is expressed in decibels (dB).
Output isolation performance is a strong function of the PCB layout. See the Layout Guidelines section on how to best optimize the isolation performance.
The TPS7A39 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A39 can be used in a phase-locked loop (PLL)-based clocking circuit that can be used for minimum phase noise, or in test and measurement systems where even small power-supply noise fluctuations reduce system dynamic range.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 68 shows a simplified output voltage noise density plot versus frequency.
For further details, see the How to Measure LDO Noise white paper.
Table 7 describes how the ultra-low noise floor and PSRR of the device can be improved in several ways.
PARAMETER | NOISE | PSRR | ||||
---|---|---|---|---|---|---|
LOW-FREQUENCY | MID-FREQUENCY | HIGH-FREQUENCY | LOW-FREQUENCY | MID-FREQUENCY | HIGH-FREQUENCY | |
CNR/SS | +++ | No effect | No effect | +++ | + | No effect |
CFFx | ++ | +++ | + | ++ | +++ | + |
COUTx | No effect | + | +++ | No effect | + | +++ |
|VINx| – |VOUTx| | + | + | + | +++ | +++ | ++ |
PCB layout | ++ | ++ | + | + | +++ | +++ |
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 8. The effect of the CNR/SS capacitor increases when VOUTx(NOM) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, a 10-nF to 1-µF CNR/SS is recommended.
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR.
A larger COUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high power dissipation across the die increases the output noise because of the increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and isolating VOUTx at high frequencies.
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions illustrated in Figure 69 are broken down in this section and are described in Table 8. Regions A, E, and H are where the output voltage is in steady-state. Increasing the output capacitance improves the transient response (less dip); however, the transient takes longer to recover when using a large output capacitor.
REGION | DESCRIPTION | COMMENT |
---|---|---|
A | Regulation | Regulation |
B | Output current ramping | Initial voltage dip is a result of the depletion of the output capacitor charge. |
C | LDO responding to transient | Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation. |
D | Reaching thermal equilibrium | At high load currents the LDO takes some time to heat up. During this time the output voltage changes slightly. |
E | Regulation | Regulation |
F | Output current ramping | Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase. |
G | LDO responding to transient | Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor. |
H | Regulation | Regulation |
The device features an output voltage accuracy that includes the errors introduced by the internal reference, load regulation, line regulation, process variation, and operating temperature as specified by the table. Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent (for very low output voltages this specification is in mV).
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and output voltage (|VDO| = |VINx| – |VOUTx|) that is required for regulation. When VINx drops below the required VDOx for the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is proportional to the output current because the device is operating as a resistive switch.
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the substrate of the device instead of the normal conducting channel of the pass element. This current flow, at high enough magnitudes, degrades long-term reliability of the device resulting from risks of electromigration and excess heat being dissipated across the device.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUTP > VINP + 0.3 V and VOUTN < VINN – 0.3 V:
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. Use Equation 9 to approximate PD:
Careful selection of the system voltage rails minimizes power dissipation and improves system efficiency. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. According to Equation 10, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (θJA) of the combined PCB, device package, and the temperature of the ambient air (TA).
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The θJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, θJA is actually the sum of the WSON package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper.
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the Electrical Characteristics table and are used in accordance with Equation 11.
where
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
Input supply | Must operate off of 5-V input | 5-V input supply |
Output supply | Must have a 5-V and –5-V output | ±5-V output, ±2% accuracy |
Positive output current | Capable of sourcing 50 mA on positive output | 50 mA (sourcing) |
Negative output current | Capable of sinking 50 mA on negative output | 50 mA (sinking) |
Isolation from 5-V supply | Must be isolated from input supply | Isolated through center tapped transformer |
Efficiency | Must have > 80% efficiency at 100 mA(1) | 85% efficiency when IOUTN = –50 mA and IOUTP = 50 mA |
This design incorporates a push-pull driver for center-tapped transformers that takes a single-ended supply and converts the supply to an isolated split rail design. The SN6505B provides a simple small-form factor isolated supply. The input voltage of the SN6505B can vary from 2.25 V to 5 V, which allows for use with a wide range of input supplies. The output voltage can be adjusted through the turns ratio of the transformer. Based on the choice of the transformer this design can be used to create output voltages from ±3.3 V to ±15 V. In this design the SN6505B was paired with the 750315371 center-tapped transformer from Wurth Electronics™. This transformer has a turns ratio of 1:1.1 and an isolation rating of 2500 VRMS (the total system isolation was never tested).
To create the isolated supply, the SN6505B uses a center-tapped transformer. A full bridge rectifier and capacitors are required to regulate the signal before reaching the LDO because of the alternating nature of the input signal. TI recommends having a fast switching and low forward voltage diode to improve efficiency because of how fast the SN6505 switches; Schottky diodes work well. Figure 73 shows the switching nodes of the SN6505 D1 and D2 and also shows where the transformer connects to the full bridge rectifier TP1 and TP2. Figure 73 shows the switching waveforms across the rectifier diodes.
Equation 12 shows how the efficiency of the system can be measured by taking the output power and dividing by the input power. IOUTP = |IOUTN| = IOUT / 2 because this system has two output rails to simplify the efficiency measurement. When the necessary parameters are measured, and by using Equation 12, the overall system efficiency can be plotted as in Figure 74. Figure 74 shows the overall system efficiency for this design, at the maximum output current of 100 mA (IOUTP = 50 mA, IOUTN = –50 mA) the efficiency of the system is 85%.
Equation 13 and Equation 14 calculate the values of the feedback resistors.
For this design the recommended 10-kΩ resistors are used for R2P and R2N. R1P and R1N can be calculated by substituting R2P and R2N into Equation 15 and Equation 16 because R2P and R2N are already selected
After solving for Equation 15 and Equation 16, the closest one percent resistors are selected, R1N = 42.2 kΩ and R1P = 32.4 kΩ.
IOUT = IOUTP + |IOUTN|, IOUTP = |IOUTN| |
A common problem in analog-to-digital converters (ADCs) is that as the input signal approaches the edge of the range of the ADC, the signal begins to become distorted. Often times this is not because of a limitation of the ADC, but is a result of the analog front-end (AFE). In the AFE, the signal begins to approach the rails of the op amp and the signal begins to lose linearity and becomes distorted. This distortion is because when the rail-to-rail op amp begins to enter the nonlinear region of operation within 100 mV of the rail, the signal-to-noise ratio (SNR) starts to degrade and the total harmonic distortion (THD) of the ADC increases. To prevent the op amp from exiting the linear region of operation, the design must use a power supply that can generate rails 200 mV above and below the input range of the ADC.
In this design, the ADS8900B is used as the ADC. This ADC features a differential input, so from a 5-V reference the ADC is able to encode values between ±5 V. In many applications, single-supply op amps are powered with rails from 0 V to 5 V, which causes the input signal to become distorted when the full range signal is applied. The FFT of a 10-VPP (peak-to-peak) sine wave using a single 5-V rail to bias the amplifiers is illustrated in Figure 79. In this test the SNR was calculated to be 54.89 dB and the THD was calculated to be –40.68 dB.
There is a simple solution to improve the SNR and THD of the ADC: bias the amplifiers in the analog front end with a 5.2-V rail and a –0.2-V rail. Using these rails allows the amplifier to operate in the linear region in the 0-V to 5-V range needed by the ADC. The FFT of a 10-VPP sine wave using a 5.2-V rail and a –0.2-V rail is illustrated in Figure 80. In this test the SNR was calculated to be 102.535 dB and the THD was calculated to be –121.66 dB. Using –0.2-V and 5.2-V rail voltages still allows for common 5-V (5.5 V max) op amps to be used in the design.
The TPS7A39 has an innovative feature of regulating the negative rail down to zero volts. This regulation is achieved by using an inverting amplifier and using the positive-buffered reference as the input signal to the amplifier. Regulating to –0.2 V eliminates the nonlinearity and distortion present when using the full rail range of the amplifiers.
Use Equation 17 and Equation 18 to calculate the values of the feedback resistors:
For this design the recommended 10-kΩ resistors are used for R2P and R2N. R1P and R1N can be calculated by substituting R2P and R2N into Equation 19 and Equation 20 because R2P and R2N are already selected.
After solving for Equation 19 and Equation 20, the closest one percent resistors are selected, R1N = 1.69 kΩ and R1P = 34 kΩ.
fIN = 1 kHz, VPP = 10.0 V |
fIN = 1 kHz, VPP = 10.0 V |
The input supply for the LDO must be within the recommended operating conditions. The input voltage must provide adequate headroom in order for the device to have a regulated output. Place the 10-µF input capacitors as close to the device as possible. If the input supply is noisy, additional input capacitors can help improve the output noise performance.
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with capacitors.
Tie the GND pin directly to the thermal pad under the device. The thermal pad must be connected to any internal PCB ground planes using multiple vias directly under the device.
Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because these circuits can impact system performance negatively, and even cause instability.
To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VIN and VOUT, with each ground plane star connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND pin of the device.
Solder pad footprint recommendations for the TPS7A39 are available at the end of this document and at www.ti.com.
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A39. The TPS7A39EVM-865 evaluation module (and related user guide) can be requested at the Texas Instruments website through the product folder or purchased directly from the TI eStore.
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS7A39 is available through the product folder under Tools & Software.
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Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
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