SBVS296B September   2017  – June 2018 TPS7A52-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Powering RF Components
      2.      Output Voltage Noise vs Frequency and Output Voltage
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS Pin)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
      3. 7.4.3 Current Limit Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Recommended Capacitor Types
        1. 8.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
        2. 8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
        3. 8.1.1.3 Feed-Forward Capacitor (CFF)
      2. 8.1.2  Soft-Start and Inrush Current
      3. 8.1.3  Optimizing Noise and PSRR
      4. 8.1.4  Charge Pump Noise
      5. 8.1.5  Current Sharing
      6. 8.1.6  Adjustable Operation
      7. 8.1.7  Power-Good Operation
      8. 8.1.8  Undervoltage Lockout (UVLO) Operation
      9. 8.1.9  Dropout Voltage (VDO)
      10. 8.1.10 Load Transient Response
      11. 8.1.11 Reverse Current Protection Considerations
      12. 8.1.12 Power Dissipation (PD)
      13. 8.1.13 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
      2. 10.1.2 RTK Package—High CTE Mold Compound
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Reference Designs
        3. 11.1.1.3 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to +150°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V(1), OUT connected to 50 Ω to GND(2), VEN = 1.1 V, CIN = 10 µF, COUT = 22 µF, CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage 0.8 V
VNR/SS NR/SS pin voltage 0.8 V
VUVLO1+(IN) Rising input supply UVLO with BIAS VIN rising with VBIAS = 3.0 V   1.02 1.09 V
VHYS1(IN) VUVLO1(IN) hysteresis VBIAS = 3.0 V   320   mV
VUVLO1-(IN) Falling input supply UVLO with BIAS VIN falling with VBIAS = 3.0 V 0.55 0.711   V
VUVLO2+(IN) Rising input supply UVLO without BIAS VIN rising   1.31 1.39 V
VHYS2(IN) VUVLO2(IN) hysteresis     253   mV
VUVLO2-(IN) Falling input supply UVLO without BIAS VIN falling  0.65 1.064   V
VUVLO+(BIAS) Rising bias supply UVLO VBIAS rising, VIN = 1.1 V   2.83 2.9 V
VUVLO-(BIAS) Falling bias supply UVLO VBIAS falling, VIN = 1.1 V 2.45 2.531   V
VHYS(BIAS) VUVLO(BIAS) hysteresis VIN = 1.1 V   290   mV
VOUT  Output voltage Range 0.8  5.2 V
Accuracy 0.8 V ≤ VOUT ≤ 5.15 V, 5 mA ≤ IOUT ≤ 2 A, over VIN , –40℃ < TJ < 150℃ –2.0%   1.0%
Accuracy with BIAS VIN = 1.1 V, 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V,  –40℃ < TJ < 150℃ –1.75%   0.75%
Accuracy 0.8 V ≤ VOUT ≤ 5.15 V, 5 mA ≤ IOUT ≤ 2 A, over VIN,  –40℃ < TJ < 125℃ –1%   1%
Accuracy with BIAS VIN = 1.1 V, 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V, –40℃ < TJ < 125℃ –0.75%   0.75%
ΔVOUT/ ΔVIN                   Line regulation             IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.03 mV/V
ΔVOUT/ ΔIOUT Load regulation 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V		 0.07 mV/A
5 mA ≤ IOUT ≤ 2 A 0.08
5 mA ≤ IOUT ≤ 2 A, VOUT = 5.2 V 0.04
VDO Dropout voltage  RGR package VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3% 103 190 mV
VIN = 5.3 V, IOUT = 2 A, VFB = 0.8 V – 3% 135 220
VIN = 5.5 V, IOUT = 2 A, VFB = 0.8 V – 3% 157 300
VIN = 1.1 V, 3.0 V ≤ VBIAS ≤ 6.5 V,
IOUT = 2 A, VFB = 0.8 V – 3%		 73 120
RTK package VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3% 215 mV
VIN = 5.3 V, IOUT = 2 A, VFB = 0.8 V – 3% 265
VIN = 5.5 V, IOUT = 2 A, VFB = 0.8 V – 3% 340
VIN = 1.1 V, 3.0 V ≤ VBIAS ≤ 6.5 V,
IOUT = 2 A, VFB = 0.8 V – 3%		 145
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V		 2.7 3.3 4 A
ISC Short-circuit current limit RLOAD = 20 mΩ 1.0 A
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 3 4 mA
VIN = 1.4 V, IOUT = 2 A 3.7 5
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V 25 µA
IEN EN pin current VIN = 6.5 V, VEN = 0 V and 6.5 V –0.5 0.5 µA
IBIAS BIAS pin current VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 2 A		 2.3 3.5 mA
VIL(EN) EN pin low-level input voltage
(disable device)		 0.5 V
VIH(EN) EN pin high-level input voltage
(enable device)		 1.1 V
VIT-(PG) PG pin threshold For falling VOUT 0.82VOUT 0.88VOUT 0.93VOUT V
VHYS(PG) PG pin hysteresis   0.02VOUT V
VIT+(PG) PG pin threshold For rising VOUT 0.84VOUT 0.90VOUT 0.95VOUT V
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA
(current into device)		 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, VIN = 6.5 V 4.0 6.5 10 µA
IFB FB pin leakage current VIN = 6.5 V –100 100 nA
PSRR Power-supply ripple rejection VIN – VOUT = 0.4 V,
IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF,
COUT = 22 µF		 f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V		 42 dB
f = 500 kHz, VOUT = 0.8 V, VBIAS = 5.0 V 39
f = 10 kHz,
VOUT = 5.0 V		 40
f = 500 kHz, VOUT = 5.0 V 25
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 2 A,
CNR/SS = 100 nF, CFF = 10 nF, COUT = 22 µF		 4.4 µVRMS
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 2 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 22 µF		 7.7
TSD Thermal shutdown temperature Shutdown, temperature increasing   160   °C
Reset, temperature decreasing   140  
(1) VOUT(nom) is the expected VOUT value set by the external feedback resistors.
(2) This 50-Ω load is disconnected when the test conditions specify an IOUT value.