The TPS7A54 is a low-noise (4.4 µVRMS), low-dropout linear regulator (LDO) capable of sourcing 4 A with only 175 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.1 V using an external resistor divider.
The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A54 an excellent choice to power noise-sensitive components such as those found in radar power and infotainment applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering RF amplifiers, radar sensors, and chipsets. Specifically, RF amplifiers benefit from the high performance and 5.0-V output capability of the device.
For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A54 provides optimal system performance.
As an adjustable voltage regulator, there is versatility in design of the TPS7A54 that makes the device a component of choice for analog loads such as voltage-controlled oscillator (VCO), analog-to-digital converter (ADC), digital-to-analog converter (DAC), and imaging sensors and for digital loads such as serializer/deserializer (SerDes), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A54 | VQFN (12) | 2.20 mm × 2.50 mm |
Changes from * Revision (November 2019) to A Revision
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | NO. | I/O | |
BIAS | 5 | I | BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance for VIN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be left floating or tied to ground. |
EN | 3 | I | Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN or BIAS. |
FB | 9 | I | Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can disrupt PG (power good) functionality. |
GND | 6, 7, 12 | — | Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
IN | 1, 2 | I | Input supply voltage pin. A 10-µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible. |
NR/SS | 4 | — | Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. |
OUT | 10, 11 | O | Regulated output pin. A 47-µF or larger ceramic capacitor (25 µF or greater of capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to the load. |
PG | 8 | O | Active-high, power-good pin. An open-drain output indicates when the output voltage reaches VIT(PG) of the target. The use of a feed-forward capacitor can disrupt PG (power good) functionality. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN, BIAS, PG, EN | –0.3 | 7.0 | V |
SNS, OUT | –0.3 | VIN + 0.3(2) | ||
NR/SS, FB | –0.3 | 3.6 | ||
Current | OUT | Internally limited | A | |
PG (sink current into device) | 5 | mA | ||
Temperature | operating junction, TJ | –55 | 150 | °C |
storage, Tstg | –55 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input supply voltage range | 1.1 | 6.5 | V | |
VBIAS | Bias supply voltage range | 3.0 | 6.5 | V | |
VOUT | Output voltage range(1) | 0.8 | 5.15 | V | |
VEN | Enable voltage range | 0 | 6.5 | V | |
IOUT | Output current | 0 | 4 | A | |
CIN | Input capacitor | 22 | 47 | 3000 | µF |
COUT | Output capacitor | 22 | 47 | 3000 | µF |
RPG | Power-good pullup resistance | 1 | 100 | kΩ | |
CNR/SS | NR/SS capacitor | 10 | nF | ||
CFF | Feed-forward capacitor | 10 | nF | ||
R1 | Top resistor value in feedback network for adjustable operation | 12.1 | kΩ | ||
R2 | Bottom resistor value in feedback network for adjustable operation | 160(2) | kΩ | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS7A54 | UNIT | ||
---|---|---|---|---|
RPS (VQFN)(2) | RPS (VQFN)(3) | |||
12 PINS | 12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 68.7 | 46.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 43.8 | 43.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 19.3 | N/A | °C/W |
ΨJT | Junction-to-top characterization parameter | 1.3 | 4.5 | °C/W |
ΨJB | Junction-to-board characterization parameter | 18.9 | 22 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4.2 | 11.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VFB | Feedback voltage | 0.8 | V | |||
VNR/SS | NR/SS pin voltage | 0.8 | V | |||
VUVLO+(IN) | Rising input supply UVLO with BIAS | VIN rising with VBIAS = 3 V | 1.02 | 1.085 | V | |
VUVLO-(IN) | Falling input supply UVLO with BIAS | VIN falling with VBIAS = 3 V | 0.55 | 0.7 | V | |
VUVLO+(IN) | Rising input supply UVLO without BIAS | VIN rising | 1.31 | 1.39 | V | |
VUVLO-(IN) | Falling input supply UVLO without BIAS | VIN falling | 0.65 | 1.057 | V | |
VUVLO+(BIAS) | Rising bias supply UVLO | VBIAS rising, VIN = 1.1 V | 2.83 | 2.9 | V | |
VUVLO-(BIAS) | Falling bias supply UVLO | VBIAS falling, VIN = 1.1 V | 2.45 | 2.54 | V | |
VOUT | Output voltage range | 0.8 | 5.1 | V | ||
Output voltage accuracy | 1.4 V ≤ VIN ≤ 6.5 V,
0.8 V ≤ VOUT ≤ 5.1 V, 5 mA ≤ IOUT ≤ 4 A |
-0.75 | 0.75 | % | ||
VIN =1.1 V,
5 mA ≤ IOUT ≤ 4 A, 3 V ≤ VBIAS ≤ 6.5 V |
-0.5 | 0.5 | ||||
DVOUT/ΔVIN | Line regulation | IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V | 0.03 | mV/V | ||
DVOUT/ΔVIN | Load regulation | 5 mA ≤ IOUT ≤ 4 A,
3 V ≤ VBIAS ≤ 6.5 V, VIN = 1.1 V |
0.07 | mV/A | ||
5 mA ≤ IOUT ≤ 4 A | 0.012 | |||||
VOS | Error amplifier offset voltage | VIN = 1.4V, IOUT = 5mA;
-40℃ ≤ TJ ≤ +125℃ |
-2.5 | 2.5 | mV | |
VDO | Dropout voltage | VIN = 1.4 V, IOUT = 4 A,
VFB = 0.8 V – 3% |
140 | 235 | mV | |
VIN = 5.5 V, IOUT = 4 A,
VFB = 0.8 V – 3% |
250 | 415 | ||||
VIN = 5.7 V, IOUT = 4 A,
VFB = 0.8 V – 3% |
330 | 565 | ||||
VIN = 1.1 V,
3.0 V ≤ VBIAS ≤ 6.5 V, IOUT = 4 A, VFB = 0.8 V – 3% |
85 | 175 | ||||
ILIM | Output current limit | VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V |
4.6 | 5.2 | 5.9 | A |
ISC | Short-circuit current limit | RLOAD = 20 mΩ | 2 | A | ||
IGND | GND pin current | VIN = 6.5 V, IOUT = 5 mA | 2.8 | 4 | mA | |
VIN = 1.4 V, IOUT = 4 A | 4.8 | 6 | ||||
Shutdown, PG = open, VIN = 6.5 V,
VEN = 0.5 V |
25 | µA | ||||
IEN | EN pin current | VIN = 6.5 V,
VEN = 0 V and 6.5 V |
0.5 | µA | ||
IBIAS | BIAS pin current | VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 4 A |
2.3 | 3.5 | mA | |
VIL(EN) | EN pin low-level input voltage (disable device) | 0 | 0.5 | V | ||
VIH(EN) | EN pin high-level input voltage (enable device) | 1.1 | 6.5 | V | ||
VIT-(PG) | Falling PG pin threshold | For falling VOUT | 82% × VOUT | 88.3% × VOUT | 93% × VOUT | V |
VIT+(PG) | Rising PG pin threshold | For rising VOUT | 84% × VOUT | 89.3% × VOUT | 95% × VOUT | V |
VOL(PG) | PG pin low-level output voltage | VOUT < VIT(PG),
IPG = –1 mA (current into device) |
0.4 | V | ||
Ilkg(PG) | PG pin leakage current | VOUT > VIT(PG), VPG = 6.5 V | 1 | µA | ||
INR/SS | NR/SS pin charging current | VNR/SS = GND, VIN = 6.5 V | 4 | 6.2 | 9 | µA |
IFB | FB pin leakage current | VIN = 6.5 V | 100 | nA | ||
RNR | NR resistor value | 250 | kΩ | |||
PSRR | Power-supply rejection ratio | VIN – VOUT = 0.5 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF, f = 10 kHz |
42 | dB | ||
VIN – VOUT = 0.5 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF, f = 500 kHz |
39 | |||||
Vn | Output noise voltage | Bandwidth = 10 Hz to 100 kHz,
VIN = 1.1 V, VOUT = 0.8 V, VBIAS = 5 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF |
4.4 | µVRMS | ||
Bandwidth = 10 Hz to 100 kHz,
VOUT = 5 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF |
8.4 | |||||
Tsd+ | Thermal shutdown temperature increasing | Shutdown, temperature increasing | 160 | °C | ||
Tsd- | Thermal shutdown temperature decreasing | Reset, temperature decreasing | 140 | °C |
VIN = 1.2 V, VBIAS = 5 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
VIN = 1.4 V, IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
VIN = VOUT + 0.4 V, VBIAS = 5.0 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
VIN = VOUT + 0.4 V, VOUT = 1 V, IOUT = 4 A,
CNR/SS = 10 nF, CFF = 10 nF |
VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz |
IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz |
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A, sequencing with a DC/DC converter and PG, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = 10 nF, RMS noise BW = 10 Hz to 100 kHz |
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CFF = 10 nF |
IOUT, DC = 100 mA, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs |
VIN = 1.2 V, VBIAS = 5.0 V, COUT = 47 µF || 10 µF || 10 µF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs |
IOUT = 4 A, VBIAS = 5 V |
VIN = 1.1 V, VBIAS = 3 V |
VIN = 1.1 V, VBIAS = 5 V |
VOUT = 0.8 V, VBIAS = 0 V, IOUT = 5 mA |
VIN = 1.1 V, IOUT = 5 mA |
VIN = 1.1 V |
VIN = 1.4 V, 6.5 V |
VIN = 6.5 V |
VIN = 1.1 V, VBIAS = 3 V |
IOUT = 4 A, VBIAS = 5 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
IOUT = 1 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
VIN = VOUT + 0.6 V,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF |
VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = 10 nF, CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz |
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz |
VIN = 5.6 V, IOUT = 4 A,
COUT = 47 µF || 10 µF || 10 µF, CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz |
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate = 1 A/µs, CNR/SS = CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF |
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 4 A,
COUT = 47 µF || 10 µF || 10 µF, CNR/SS = CFF = 10 nF |
IOUT = 4 A, VBIAS = 0 V | ||
VIN = 1.4 V, VBIAS = 0 V |
VIN = 5.5 V |
VIN = 1.4 V, VBIAS = 0 V |
VBIAS = 0 V, IOUT = 5 mA |
VBIAS = 0 V |
VBIAS = 0 V |
VIN = 1.1 V |
The TPS7A54 is a high-current (4 A), low-noise (4.4 µVRMS), high accuracy (1%) low-dropout linear voltage regulator with an input range of 1.1 V to 6.5 V and an output voltage range of 0.8 V to 5.1 V. The TPS7A54 has an integrated charge pump for ease of use, and an external bias rail to allow for the lowest dropout across the entire output voltage range. Table 1 categorizes the functions shown in the Functional Block Diagram. These features make the TPS7A54 a robust solution to solve many challenging problems by generating a clean, accurate power supply in a variety of applications.
VOLTAGE REGULATION | SYSTEM START-UP | INTERNAL PROTECTION |
---|---|---|
High accuracy | Programmable soft start | Foldback current limit |
Low-noise, high-PSRR output | No sequencing requirement between BIAS, IN, and EN | Thermal shutdown |
Fast transient response | Power-good output | |
Start-up with negative bias on OUT |
An low-dropout regulator (LDO) functions as a class-B amplifier, as shown in Figure 40, in which the input signal is the internal reference voltage (VREF). VREF is designed to have very-low bandwidth at the input to the error amplifier through the use of a low-pass filter (VNR/SS).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes from the combination of the output capacitor and pass element. The pass element also presents a high input impedance to the source voltage when operating as a current source. A positive LDO can only source current because of the class-B architecture.
This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision band-gap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation required by the device to regulate the output voltage at a given current level, thereby improving system efficiency. These features combine to make this device a good approximation of an ideal voltage source.
NOTE:
VOUT = VREF × (1 + R1 / R2).The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output current (load transient) resulting from the LDO high-input impedance and low output-impedance across frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR) and, when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac (small-signal) and large-signal conditions.
The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor (CNR/SS) and feed-forward capacitor (CFF) easily reduce the device noise floor and improve PSRR.
In many different applications, the power-supply output must turn on within a specific window of time to either provide proper operation of the load or to minimize the loading on the input supply or other sequencing requirements. The LDO start-up is well-controlled and user-adjustable, solving the demanding requirements faced by many power-supply design engineers in a simple fashion.
Soft start directly controls the output start-up time and indirectly controls the output current during start-up (inrush current).
As shown in Figure 41, the external capacitor at the NR/SS pin (CNR/SS) sets the output start-up time by setting the rise time of the internal reference (VNR/SS).
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of the high power levels inherent in a PDN, and the variations between all of the supplies. As shown in Figure 42 and Table 2, the LDO turnon and turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits (UVLO1,2(IN) and UVLOBIAS).
INPUT VOLTAGE | BIAS VOLTAGE | ENABLE STATUS | LDO STATUS | ACTIVE DISCHARGE | POWER GOOD |
---|---|---|---|---|---|
VIN ≥ VUVLO_1,2(IN) | VBIAS ≥ VUVLO(BIAS) | EN = 1 | On | Off | PG = 1 when VOUT ≥ VIT(PG) |
EN = 0 | Off | On | PG = 0 | ||
VBIAS < VUVLO(BIAS) + VHYS(BIAS) | EN = don't care | Off | On(1) | ||
VIN < VUVLO_1,2(IN) – VHYS1,2(IN) | BIAS = don't care | Off | |||
IN = don't care | VBIAS ≥ VUVLO(BIAS) | Off |
VBIAS is not intended to be used dynamically when the IN rail is being powered up. If the BIAS rail is powered down when the IN rail is greater than 1.4 V, the PG output can trip. If the BIAS rail is powered up after the IN rail for VIN ≥ 1.4 V, a non-monotonic startup can occur.