SBVS360A February   2020  – November 2020 TPS7B85-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Power-Good (PG)
        1. 7.3.2.1 Adjustable Power-Good (PGADJ)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Sense Comparator
      5. 7.3.5 Undervoltage Lockout
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 SI Pin
        1. 8.1.6.1 Calculating the Sense Input (SI) Pin Threshold
        2. 8.1.6.2 Different Uses for the Sense Input Pin
          1. 8.1.6.2.1 Monitoring Input Voltage
          2. 8.1.6.2.2 Creating OV and UV Power-Good
          3. 8.1.6.2.3 Monitoring a Separate Supply Voltage
      7. 8.1.7 Pulling Up the SO and PG Pins to a Different Voltage
      8. 8.1.8 Power-Good
        1. 8.1.8.1 Setting the Adjustable Power-Good Threshold
        2. 8.1.8.2 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

6.5 Electrical Characteristics

specified at TJ = –40°C to +150°C, VIN = 13.5 V,  IOUT = 0 mA, COUT = 2.2 µF, 1 mΩ < COUT ESR < 2 Ω,  CIN = 1 µF, and VEN = 2 V (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Regulated output accuracy VIN = VOUT + 500 mV to
40 V,
IOUT = 100 µA to 150 mA (1) 		TJ = 25ºC –0.5 0.5 %
TJ = –40°C to +150ºC –0.75 0.75
ΔVOUT(ΔVIN) Line regulation Change in percent of output voltage VIN = VOUT + 500 mV to 40 V, 
IOUT = 100 µA		 0.2 %
ΔVOUT(ΔIOUT) Load regulation Change in percent of output voltage VIN = VOUT + 500 mV, IOUT = 100 µA to
150 mA 		0.2
ΔVOUT Load transient response settling time(2) (3) COUT = 10 µF COUT = 10 µF 100 µs
Load transient response
overshoot, undershoot(3) 		IOUT = 45 mA to 105 mA –2% 10% %VOUT
IOUT = 0 mA to 150 mA –10%
IQ Quiescent current VIN = VOUT + 500 mV to
40 V, IOUT = 0 mA
TJ = 25ºC
 		 18 21 µA
TJ = –40°C to +150ºC 26
IOUT = 500 µA TJ = –40°C to +150ºC 35
ISHUTDOWN Shutdown supply current (IGND) VEN = 0 V TJ = 25ºC 2.5 µA
TJ = –40°C to +150ºC 4
VDO Dropout voltage IOUT ≤ 1 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) x 0.95 43 mV
IOUT = 105 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 125 175
IOUT = 150 mA, VOUT ≥ 3.3 V, VIN = VOUT(NOM) 155 225
VUVLO(RISING) Rising input supply UVLO VIN rising 2.6 2.7 2.82 V
VUVLO(FALLING) Falling input supply UVLO VIN falling 2.38 2.5 2.6 V
VUVLO(HYST) VUVLO hysteresis 230 mV
VIL Enable logic input low level 0.7 V
VIH Enable logic input high level 2 V
IEN EN pin current VEN = VIN = 13.5 V 50 nA
ICL Output current limit VIN = VOUT(nom) + 1 V, VOUT short to
90% x VOUT(NOM) 		180 220 260 mA
PSRR Power-supply ripple rejection VIN - VOUT = 500 mV, frequency = 1 kHz,
IOUT = 150 mA		 55 dB
Vn Output noise voltage VOUT = 3.3 V, BW = 10 Hz to 100 kHz 280 µVRMS
VSI(HIGH) Sense input threshold high VSI rising 1.17 1.21 1.25 V
VSI(LOW) Sense input threshold low VSI falling 1.07 1.12 1.15 V
VSI(HYST) Sense input switching hysteresis 90 mV
ISI Sense input current VSI = 40 V 0.015 1.5 µA
RSO Sense output internal pullup resistor 10 30 50 kΩ
VSO(OL) Sense output low voltage VSI ≤ 1.07 V, VIN ≥ 3 V 0.4 V
RPG Power-good internal pullup resistor 10 30 50 kΩ
VPG(OL) PG pin low level output voltage VOUT ≤ 0.83 x VOUT 0.4 V
VPG(TH,RISING) Default power-good threshold VOUT rising, PGADJ pin shorted to ground 85 95 %VOUT
VPG(TH,FALLING) VOUT falling, PGADJ pin shorted to ground 83 93
VPG(HYST) Power-good hysteresis 2.5 %VOUT
VPGADJ (TH,FALLING) Switching voltage for the power-good adjust pin VOUT falling, PGADJ falling  0.97 1 1.030 V
VPGADJ(HYST) PGADJ hysteresis 5 35 50 mV
VDLY(TH) Threshold to release power-good high Voltage at delay pin rising 1.17 1.21 1.25 V
IDLY(CHARGE) Delay capacitor charging current VDLY = 1 V 1 1.5 2 µA
TSD(SHUTDOWN) Junction shutdown temperature 175 °C
TSD(HYST) Hysteresis of thermal shutdown 20 °C
(1) Power dissipation is limited to 2W for IC production testing purposes. The power dissipation can be higher during normal operation. Please see the thermal dissipation section for more information on how much power the device can dissipate while maintaining a junction temperature below 150℃.
(2) The settling time is measured from when IOUT is stepped from 45mA to 105 mA to when the output voltage recovers to
VOUT = VOUT(nom) - 5 mV.
(3) This specification is specified by design.