SBVS366A July   2018  – October 2021 TPS3430

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 CRST
      2. 7.3.2 Window Watchdog
        1. 7.3.2.1 SET0 and SET1
          1. 7.3.2.1.1 Enabling the Window Watchdog
          2. 7.3.2.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
          3. 7.3.2.1.3 SET0 and SET1 During Normal Watchdog Operation
      3. 7.3.3 Window Watchdog Timer
        1. 7.3.3.1 CWD
        2. 7.3.3.2 WDI Functionality
        3. 7.3.3.3 WDO Functionality
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR ( VDD < VPOR)
      2. 7.4.2 VDD is Above VPOR And Below VDD (min)( VPOR < VDD < VDD (min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD (min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CRST Delay
        1. 8.1.1.1 Factory-Programmed Watchdog Reset Delay Timing
        2. 8.1.1.2 CRST Programmable Watchdog Reset Delay
      2. 8.1.2 CWD Functionality
        1. 8.1.2.1 Factory-Programmed Timing Options
        2. 8.1.2.2 CWD Adjustable Capacitor Watchdog Timeout
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Microcontroller with Watchdog Timer - Design 1
        1. 8.2.1.1 Design Requirements - Design 1
        2. 8.2.1.2 Detailed Design Procedure - Design 1
          1. 8.2.1.2.1 Meeting the Minimum Watchdog Reset Delay - Design 1
          2. 8.2.1.2.2 Setting the Watchdog Window - Design 1
          3. 8.2.1.2.3 Calculating the WDO Pull-up Resistor - Design 1
      2. 8.2.2 Monitoring Microcontroller with a Programmed Window Watchdog Timer - Design 2
        1. 8.2.2.1 Design Requirements - Design 2
        2. 8.2.2.2 Detailed Design Procedure - Design 2
          1. 8.2.2.2.1 Meeting the Minimum Watchdog Reset Delay - Design 2
          2. 8.2.2.2.2 Setting the Watchdog Window - Design 2
          3. 8.2.2.2.3 Calculating the WDO Pull-up Resistor - Design 2
      3. 8.2.3 Monitoring Microcontroller with a Latching Window Watchdog Timer - Design 3
        1. 8.2.3.1 Design Requirements - Design 3
        2. 8.2.3.2 Detailed Design Procedure - Design 3
          1. 8.2.3.2.1 Meeting the Latching Output Requirement - Design 3
          2. 8.2.3.2.2 Setting the Watchdog Window - Design 3
        3. 8.2.3.3 Application Curve - Design 3
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-4A557685-FB8B-4730-8014-FF2D154FACAA-low.gifFigure 5-1 DRC Package
3-mm × 3-mm VSON-10
Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
VDD1 1 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.
CWD 2 I Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further enables the selection of the preset watchdog timeouts; see the Section 6.6 table.
When using a capacitor, the TPS3430 determines the window watchdog upper boundary with Equation 4. The lower watchdog boundary is set by the SET pins, see andTable 8-5 the Section 8.1.2 section for additional information.
SET0 3 I Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog; see the Section 6.6 table.
CRST 4 I Programmable watchdog reset delay pin. Connect a capacitor between this pin and GND to program the watchdog reset delay period. This pin can also be connected by a 10-kΩ pull-up resistor to VDD, or left unconnected (NC) for various factory programmed watchdog reset delay options; see the Section 8.1.1 section.
When using an external capacitor, use Equation 1 to determine the watchdog reset delay.
GND 5 — Ground pin
SET1 6 I Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog; see the Section 6.6 table.
WDI 7 I Watchdog input. A falling transition (edge) must occur at this pin within the watchdog timeout between the lower (tWDL(max)) and upper (tWDU(min)) window boundaries in order for WDO to not assert. During power up, all pulses to WDI are ignored before tRST expires and the watchdog is disabled.
When the watchdog is not in use, the SET pins can be used to disable the watchdog. The input at WDI is ignored when WDO is low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.
WDO 8 O Watchdog open-drain active-low output. Connect WDO with a 1-kΩ to 100-kΩ resistor to VDD or another power supply. WDO goes low (asserts) when a watchdog timeout occurs. When a watchdog timeout occurs, WDO goes low (asserts) for the set WDO reset delay (tRST). When the watchdog is disabled, WDO remains logic high regardless of WDI.
NC 9 NC This pin is no-connect and must be left floating.
VDD2 10 I Connect this pin to VDD1. The device will not function properly if VDD1 and VDD2 are not externally connected.
Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.