SBVS437C December 2022 – June 2024 TPS7A21-Q1
PRODMIX
The dynamic performance of the TPS7A21-Q1 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs potentially degrade the PSRR, noise, or transient performance of the TPS7A21-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the TPS7A21-Q1, and as close to the package as practical. Route the ground connections for CIN and COUT back to the TPS7A21-Q1 ground pin using as wide and short a copper trace as practical.
Avoid connections using long trace lengths, narrow trace widths, or connections through vias. These connections add parasitic inductances and resistance that results in inferior performance, especially during transient conditions.