SBVU073A november 2021 – june 2023 TPS7A14
The TPS7A14EVM-058 and TPS7A14EVM-095 evaluation module contains the TPS7A14 LDO with input, bias, and output capacitors installed. These four components provide the minimum required solution size, as illustrated by the white boxes in Figure 1-1 and Figure 2-6. Additional pads are available to test the LDO with additional input, bias, and output capacitors beyond what is already installed on the EVM. The TPS7A14 LDO can be enabled or disabled by using the J7 3-pin header.
Alternatively, by connecting an external function generator to TP1 (EN) and a nearby GND post (J11), the user can enable or disable the TPS7A14 LDO after VIN is applied. Figure 2-1 shows the result of the TPS7A14EVM-058 during turn on. The blue trace is the enable voltage, and the red trace is the output voltage.
If desired, a current probe can be inserted in the EVM as shown in Figure 2-2 to measure the input and output current. The slots were sized to fit most current probes, such as the LeCroy™ AP015 or CP031 current probes.
The user has two options for providing a DC load on the output of the TPS7A14. J10 can be used to place a DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and J12 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop does not sense current flowing through these connectors. In cases where very fast transient tests are performed, ringing can be observed on VIN or VOUT as a result of the parasitic inductance within the PCB of the EVM. A strip of wire placed on the exposed copper in the current path can reduce this ringing. Select the correct size of additional wire to fill the volume of the current probe. For most current probes, a 10 AWG wire can be used.
Optional kelvin sense points are provided using the SMA connectors J1 (VIN) and J2 (VOUT).