SBVU073A november   2021  – june 2023 TPS7A14

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 LDO Input/Output Connector Descriptions
      1. 2.1.1 VIN and GND
      2. 2.1.2 BIAS and GND
      3. 2.1.3 VOUT and GND
      4. 2.1.4 EN
    2. 2.2 Optional Load Transient Input/Output Connector Descriptions
      1. 2.2.1 VDD and GND
      2. 2.2.2 J13
      3. 2.2.3 J15
      4. 2.2.4 J16
      5. 2.2.5 J18
      6. 2.2.6 J19
      7. 2.2.7 J22
      8. 2.2.8 TP2, TP3, and TP4
      9. 2.2.9 TP5
    3. 2.3 TPS7A14 LDO Operation
    4. 2.4 Optional Load Transient Circuit Operation
  6. 3Board Layout
  7. 4TPS7A14EVM Schematic
  8. 5Bill of Materials
  9. 6Revision History

2.2.8 TP2, TP3, and TP4

TP2, TP3, and TP4 allow the user to measure the gate drive resistances R8 and R9 when power is turned off to the EVM.