SBVU075 April   2022

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 LDO Input and Output Connector Descriptions
      1. 2.1.1 VIN and GND
      2. 2.1.2 VOUT and GND
      3. 2.1.3 J3
      4. 2.1.4 J4 (EN)
      5. 2.1.5 J5 (CP_EN)
      6. 2.1.6 J1 (PG)
    2. 2.2 Optional Load Transient Input and Output Connector Descriptions
      1. 2.2.1 VCC and GND
      2. 2.2.2 J17
      3. 2.2.3 TP10
      4. 2.2.4 IN1
      5. 2.2.5 J15
      6. 2.2.6 TP11 and TP12
      7. 2.2.7 J6 and TP13
    3. 2.3 TPS7A57 LDO Operation
    4. 2.4 Optional Load Transient Circuit Operation
  4. 3Board Layout
  5. 4TPS7A57EVM-056 Schematics
  6. 5Bill of Materials

2.1.6 J1 (PG)

J1 (PG) is a 2-pin header used for the power-good (PG) feature of the TPS7A57 LDO.

When the 2-pin shunt is placed across the header, the PG pin is pulled up to VOUT using a 100-kΩ resistor.

For more information regarding PG functionality, see the TPS7A57 data sheet.