SBVU075 April   2022

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 LDO Input and Output Connector Descriptions
      1. 2.1.1 VIN and GND
      2. 2.1.2 VOUT and GND
      3. 2.1.3 J3
      4. 2.1.4 J4 (EN)
      5. 2.1.5 J5 (CP_EN)
      6. 2.1.6 J1 (PG)
    2. 2.2 Optional Load Transient Input and Output Connector Descriptions
      1. 2.2.1 VCC and GND
      2. 2.2.2 J17
      3. 2.2.3 TP10
      4. 2.2.4 IN1
      5. 2.2.5 J15
      6. 2.2.6 TP11 and TP12
      7. 2.2.7 J6 and TP13
    3. 2.3 TPS7A57 LDO Operation
    4. 2.4 Optional Load Transient Circuit Operation
  4. 3Board Layout
  5. 4TPS7A57EVM-056 Schematics
  6. 5Bill of Materials

3 Board Layout

Figure 3-1 through Figure 3-8 illustrate the board layout for the TPS7A57EVM-056 PCB.

The TPS7A57EVM-056 dissipates power, which may cause some components to experience an increase in temperature. The TPS7A57 LDO, LMG1020YFFR gate driver, and pulsed resistors R10, R11, R12, R13, and R14 are most at risk of raising to a high junction temperature during normal operation.

Figure 3-1 Top Assembly Layer and Silkscreen
Figure 3-3 Layer 2
Figure 3-5 Layer 4
Figure 3-7 Bottom Layer Routing
Figure 3-2 Top Layer Routing
Figure 3-4 Layer 3
Figure 3-6 Layer 5
Figure 3-8 Bottom Assembly Layer and Silkscreen