SBVU081 june   2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Before You Begin
  5. 2EVM Setup
    1. 2.1 Inputs/Outputs Connectors and Jumper Descriptions
      1. 2.1.1  J1 – IN
      2. 2.1.2  J2 – OUT
      3. 2.1.3  J3
      4. 2.1.4  TP1 – IN
      5. 2.1.5  TP2 – PG
      6. 2.1.6  TP3 – SNS
      7. 2.1.7  TP4 – PG_FB
      8. 2.1.8  TP5 – OUT
      9. 2.1.9  TP6 – EN
      10. 2.1.10 TP7 – GND
      11. 2.1.11 TP8 – GND
    2. 2.2 Soldering Guidelines
    3. 2.3 Equipment Connections
  6. 3Operation
  7. 4Schematic
  8. 5PCB Layout
  9. 6Bill of Materials

PCB Layout

Figure 5-1 to Figure 5-5 illustrate the PCB layout for this EVM.

GUID-20230601-SS0I-XLNR-KXXF-ZKBKTLRS8W5Z-low.svgFigure 5-1 Assembly Layer
GUID-20230601-SS0I-601G-RHBV-NF0JJWDT3WCD-low.svgFigure 5-3 First Middle Layer
GUID-20230601-SS0I-HSK8-RCSV-FVJHV2JVSR51-low.svgFigure 5-5 Bottom Layer Routing
GUID-20230601-SS0I-HV4N-DHDS-JZ1DKGLFJKJF-low.svgFigure 5-2 Top Layer Routing
GUID-20230601-SS0I-PTHG-JBHG-XNZ7RBG9ZZWG-low.svgFigure 5-4 Second Middle Layer