SBVU082 june   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 LDO Input/Output Connector Descriptions
        1. 2.1.1.1 VIN and GND
        2. 2.1.1.2 BIAS and GND
        3. 2.1.1.3 VOUT and GND
        4. 2.1.1.4 EN
      2. 2.1.2 Optional Load Transient Input/Output Connector Descriptions
        1. 2.1.2.1 VDD and GND
        2. 2.1.2.2 J13
        3. 2.1.2.3 J15
        4. 2.1.2.4 J16
        5. 2.1.2.5 J18
        6. 2.1.2.6 J19
        7. 2.1.2.7 J22
        8. 2.1.2.8 TP2, TP3, and TP4
        9. 2.1.2.9 TP5
      3. 2.1.3 TPS7A15 LDO Operation
      4. 2.1.4 Optional Load Transient Circuit Operation
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 Board Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1.     Trademarks

2.1.3 TPS7A15 LDO Operation

The TPS7A15EVM-096 evaluation module contains the TPS7A15 LDO with input, bias, and output capacitors installed. These four components provide the minimum required solution size, as illustrated by the white boxes in Figure 1-1. Additional pads are available to test the LDO with additional input, bias, and output capacitors beyond what is already installed on the EVM. The TPS7A15 LDO can be enabled or disabled by using the J7 3-pin header.

  1. Place a 2-pin shunt across the header to tie VIN to EN to enable the device.
  2. Place a 2-pin shunt across the header to tie GND to EN to disable the device.

Alternatively, by connecting an external function generator to TP1 (EN) and a nearby GND post (J11), the user can enable or disable the TPS7A15 LDO after VIN is applied. Figure 3-1 shows the result of the TPS7A15EVM-096 during turn on. The blue trace is the enable voltage, and the red trace is the output voltage.

GUID-20230629-SS0I-FQL0-DZPC-LV5KD9SSNK7C-low.png Figure 2-1 TPS7A15EVM-096 Turn On

If desired, a current probe can be inserted in the EVM as shown in Figure 3-2 to measure the input and output current. The slots were sized to fit most current probes, such as the LeCroy™ AP015 or CP031 current probes.

GUID-20230629-SS0I-LT0F-SG5T-QKXZLXW73G9J-low.png Figure 2-2 TPS7A15EVM-096 With Current Probes Attached

The user has two options for providing a DC load on the output of the TPS7A15. J10 can be used to place a DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and J12 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop does not sense current flowing through these connectors. In cases where very fast transient tests are performed, ringing can be observed on VIN or VOUT as a result of the parasitic inductance within the PCB of the EVM. A strip of wire placed on the exposed copper in the current path can reduce this ringing. Select the correct size of additional wire to fill the volume of the current probe. For most current probes, a 10 AWG wire can be used.

WARNING: The sensors of some current probes are tied to GND and cannot come into contact with energized conductors. See the user manual of your current probe for details. If your current probe has this limitation, use a thin strip of electrical or Kapton® tape to isolate the current sense path from the current probe.

Optional kelvin sense points are provided using the SMA connectors J1 (VIN) and J2 (VOUT).