SBVU082 june   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 LDO Input/Output Connector Descriptions
        1. 2.1.1.1 VIN and GND
        2. 2.1.1.2 BIAS and GND
        3. 2.1.1.3 VOUT and GND
        4. 2.1.1.4 EN
      2. 2.1.2 Optional Load Transient Input/Output Connector Descriptions
        1. 2.1.2.1 VDD and GND
        2. 2.1.2.2 J13
        3. 2.1.2.3 J15
        4. 2.1.2.4 J16
        5. 2.1.2.5 J18
        6. 2.1.2.6 J19
        7. 2.1.2.7 J22
        8. 2.1.2.8 TP2, TP3, and TP4
        9. 2.1.2.9 TP5
      3. 2.1.3 TPS7A15 LDO Operation
      4. 2.1.4 Optional Load Transient Circuit Operation
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 Board Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1.     Trademarks

Board Layout

Figure 4-2 through Figure 4-7 illustrate the board layout for the TPS7A15EVM-096 PCB.

The TPS7A15EVM-096 dissipates power, which can cause some components to experience an increase in temperature. The TPS7A15 LDO, LMG1020YFFR gate driver, and pulsed resistors R2, R3, R4, R5, and R6 are most at risk of raising to a high junction temperature during normal operation.

GUID-20230626-SS0I-KS5F-VP7R-CH5JX6NZKJ04-low.svgFigure 3-2 Top Assembly Layer and Silk Screen
GUID-20230626-SS0I-ZTMM-DVQJ-NW5N0KCBRNWV-low.svgFigure 3-4 Layer 2
GUID-20230626-SS0I-BMFF-HJZL-46WBP1Q9T78L-low.svgFigure 3-6 Bottom Layer Routing
GUID-20230626-SS0I-QFLJ-KP6X-ZRNGJ0PHWX77-low.svgFigure 3-3 Top Layer Routing
GUID-20230626-SS0I-2DFW-PNLG-RLCBBCKM6WCB-low.svgFigure 3-5 Layer 3
GUID-20230626-SS0I-C5LT-ZFXS-RXPQLPG0NVJQ-low.svgFigure 3-7 Bottom Assembly Layer and Silk Screen