SCAS887B September   2009  – January 2016 CDCLVP2106

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: LVCMOS Input, at VCC = 2.375 V to 3.6 V
    6. 6.6  Electrical Characteristics: Differential Input, at VCC = 2.375 V to 3.6 V
    7. 6.7  Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
    8. 6.8  Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
    9. 6.9  Timing Requirements, at VCC = 2.375 V to 2.625 V
    10. 6.10 Timing Requirements, at VCC = 3 V to 3.6 V
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVPECL Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RHA Package
40-Pin VQFN
Top View
CDCLVP2106 po_cas887.gif
1. Thermal pad must be soldered to ground.

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND1, GND2 21, 30 Ground Device grounds
INP0, INN0 9, 8 Input Differential input pair or single-ended input no. 0
INP1, INN1 2, 3 Input Differential input pair or single-ended input no. 1
OUTP0 OUTN0 12, 13 Output Differential LVPECL output pair no. 0
OUTP1, OUTN1 14, 15 Output Differential LVPECL output pair no. 1
OUTP2, OUTN2 16, 17 Output Differential LVPECL output pair no. 2
OUTP3, OUTN3 18, 19 Output Differential LVPECL output pair no. 3
OUTP4, OUTN4 22, 23 Output Differential LVPECL output pair no. 4
OUTP5, OUTN5 24, 25 Output Differential LVPECL output pair no. 5
OUTP6, OUTN6 26, 27 Output Differential LVPECL output pair no. 6
OUTP7, OUTN7 28, 29 Output Differential LVPECL output pair no. 7
OUTP8, OUTN8 32, 33 Output Differential LVPECL output pair no. 8
OUTP9, OUTN9 34, 35 Output Differential LVPECL output pair no. 9
OUTP10, OUTN10 36, 37 Output Differential LVPECL output pair no. 10
OUTP11, OUTN11 38, 39 Output Differential LVPECL output pair no. 11
VAC_REF0 7 Output Bias voltage output for capacitive coupled input pair no. 0. Do not use VAC_REF at VCC < 3 V. If used, TI recommends a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA.
VAC_REF1 4 Output Bias voltage output for capacitive coupled input pair no. 1. Do not use VAC_REF at VCC < 3 V. If used, TI recommends using a 0.1-μF capacitor to GND on this pin. The output current is limited to 2 mA.
VCC 5, 6, 11, 20, 31, 40 Power 2.5-V or 3.3-V supplies for the device
NC 1, 10 — Do not connect