SCASE09
June 2024
SN74ACT138-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS Push-Pull Outputs
7.3.2
TTL-Compatible CMOS Inputs
7.3.3
Wettable Flanks
7.3.4
Clamp Diode Structure
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
8.4.2
Layout Example
Figure 8-3
Example Trace Corners for Improved Signal Integrity
Figure 8-4
Example Bypass Capacitor Placement for TSSOP and Similar Packages
Figure 8-6
Example Bypass Capacitor Placement for SOT, SC70 and Similar Packages
Figure 8-5
Example Bypass Capacitor Placement for WQFN and Similar Packages
Figure 8-7
Example Damping Resistor Placement for Improved Signal Integrity