SCASE14 September   2024 SN74AC3G98

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Electrical Characteristics
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
    5. 7.5 Combinatorial Logic Configurations
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Power Supply Recommendations
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
        2. 8.2.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.5 Combinatorial Logic Configurations

SN74AC3G98 2-to-1 data selector with inverted output2-to-1 data selector with inverted output
SN74AC3G98 2-Input NAND with 1 inverted input2-Input NAND with 1 inverted input
SN74AC3G98 2-Input NOR Gate2-Input NOR Gate
SN74AC3G98 2-Input OR with 1 inverted input2-Input OR with 1 inverted input
SN74AC3G98 Schmitt-trigger inverterSchmitt-trigger inverter
SN74AC3G98 2-Input NAND Gate2-Input NAND Gate
SN74AC3G98 2-Input AND with 1 inverted input2-Input AND with 1 inverted input
SN74AC3G98 2-Input NOR with 1 inverted input2-Input NOR with 1 inverted input
SN74AC3G98 Schmitt-trigger bufferSchmitt-trigger buffer
Figure 7-2 Logic Configurations