SCASE14
September 2024
SN74AC3G98
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Electrical Characteristics
5.4
Recommended Operating Conditions
5.5
Thermal Information
5.6
Switching Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS Push-Pull Outputs
7.3.2
CMOS Schmitt-Trigger Inputs
7.3.3
Clamp Diode Structure
7.4
Device Functional Modes
7.5
Combinatorial Logic Configurations
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.2.4
Power Supply Recommendations
8.2.5
Layout
8.2.5.1
Layout Guidelines
8.2.5.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Tape and Reel Information
11.2
Mechanical Data
1
Features
Wide operating range of 1.5V to 6V
Inputs accept voltages up to 6V
Continuous
±
24mA output drive at 5V
Supports up to
±
75mA output drive at 5V
in short bursts
Drives 50Ω transmission lines
Maximum t
pd
of
6
ns at 5V, 50pF load
Each channel is independently configurable as:
2-to-1 data selector or multiplexer with inverted output
2-input NAND or NOR gate
2-input AND, NAND, OR, or NOR gate with one inverted input
Buffer or Inverter