The TMUX582F-SEP samples were irradiated at a high dose rate of 191.178rad(Si)/s up to 30krad(Si) and then put through full electrical parametric testing on the production Automated Test Equipment (ATE). Additionally, other TMUX582F-SEP samples were irradiated at a low dose rate of 9.94e-03rad(Si)/s up to 30krad(Si) and then put through full electrical parametric testing on the production Automated Test Equipment (ATE). Both sample sets were functional and passed all electrical parametric tests with readings within data sheet electrical specification limits.

The TMUX582F-SEP LBCSOI2 process technology contains Bipolar and CMOS components. Both LDR and HDR were performed. Results showed that worst case values post-irradiation were still within pre-radiation specification limits for both HDR and LDR, hence no ELDRS effects were exhibited. Thus, HDR will be performed on each wafer lot for future RLAT testing.

In addition to the standard HDR and LDR characterization, other bias schemes were tested to verify max recommended operating voltages. Two different bias schemes were tested, one with the S1 pin set to a voltage of 22V and the second with the S1 pin set to a voltage of 60V to stress under a fault scenario. These extra bias schemes were radiated at 30krad under HDR conditions and the results show passing values for all parameters. For future RLAT requests, the 22V S1 pin bias plan will be used.