SCDS432 June   2021 TMUX646

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2-V Logic Compatible Inputs
      2. 8.3.2 Bidirectional Operation
      3. 8.3.3 Powered-Off Protection
      4. 8.3.4 Low Power Disable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
      2. 8.4.2 Low Power Disable Mode
      3. 8.4.3 Switch Enabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MIPI D-PHY Application
        2. 9.2.2.2 MIPI C-PHY Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.3 Powered-Off Protection

When the TMUX646 is powered off (VDD = 0 V) the I/Os and digital logic pins of the device remains in a high impedance state. The crosstalk, off-isolation, and leakage will remain within the electrical specifications. This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is powering up:

Figure 8-1 shows an example system containing a switch without powered-off protection with the following system level scenario.

  1. Subsystem A powers up and starts sending information to Subsystem B that remains unpowered.
  2. The I/O voltage back powers the supply rail in Subsystem B.
  3. The digital logic is back powered and turns on the switch. The signal is transmitted to Subsystem B before it is powered and damages it.

GUID-9D205138-AB85-4FD0-B78E-F52C94C610FA-low.gifFigure 8-1 System Without Powered-Off Protection

With powered-off protection, the switch prevents back powering the supply and the switch remains high-impedance. Subsystem B remains protected.

GUID-15B3A01A-18A6-4CFA-9488-E907D8AF6184-low.gifFigure 8-2 System With Powered-Off Protection

This features has the following system level benefits:

  • Protects the system from damage.
  • Prevents data from being transmitted unintentionally.
  • Eliminates the need for power sequencing solutions, reducing BOM count and cost, simplifying system design, and improving reliability.