SCEA064A June   2019  – March 2021 2N7001T , SN74AXC4T245 , SN74AXC4T774 , TXB0104

 

  1.   Trademarks
  2. 1Introduction
  3. 2Common Interfaces and 2N7001T Implementation
    1. 2.1 General Purpose Input Output (GPIO)
  4. 3Serial Peripheral Interface (SPI)
    1. 3.1 Application – SPI
  5. 4Universal Asynchronous Receive Transmit (UART)
    1. 4.1 Application – UART
  6. 5Joint Test Access Group (JTAG)
    1. 5.1 Application – JTAG
  7. 6Additional Resources
  8. 7Revision History

3 Serial Peripheral Interface (SPI)

SPI provides synchronous communication between a processor and a peripheral device. Table 3-1 shows how the SPI interface has a total of four signal lines.

Table 3-1 SPI Interface
SIGNAL DESCRIPTION DIRECTION
CLK Clock Signal Controller to Peripheral
CIPO Controller Input/Peripheral Output Peripheral to Controller
COPI Controller Output/Peripheral Input Controller to Peripheral
CS Peripheral Select Controller to Peripheral

The first is the clock (CLK), which only the controller can control. The controller can transmit one bit of data or receive one bit of data from the peripheral on each pulse of the CLK. Since SPI is full duplex, it requires one line for transmission (COPI) and one line for receiving data (CIPO), meaning it can receive and transmit at the same time. Finally, there is a line for peripheral select (CS) which activates the peripheral.

Communication occurs when the peripheral select line is held low to initiate communication, and then one bit of data is transmitted or received on each clock pulse. This communication is only possible if the peripheral device and the processor are operating at the same voltage levels. Since this is usually not the case, the 2N7001T can be used to provide a unidirectional level shift for the CIPO line. SN74AXC4T245 Four-bit Bus Transceiver with Configurable Voltage Translation and Tri-State Outputs data sheet shows how the three other lines that are operating in the opposite direction can be level shifted using the SN74AXC4T245, which is a 4-bit direction controlled level shifter. The 2N7001T can easily operate with data rates of up to 100 Mbps, which is usually within the recommended communication speeds for SPI interface. Alternatively, the SN74AXC4T774 or TXB0104 devices can work as a single chip solution.