SCEA065B November 2018 – March 2021 SN74AVC4T774 , SN74AXC1T45 , SN74AXC4T245 , SN74AXC4T774 , SN74AXC8T245 , SN74AXC8T245-Q1 , SN74AXCH1T45 , SN74AXCH4T245 , SN74AXCH8T245
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The AXC family of devices belong to TI's direction-controlled level translator family. These voltage translators use two separate configurable power supply rails to up- or down-translate incoming signals. The AXC translators are designed for an ultra-low VCC range of 0.65 V to 3.6 V, making them the lowest voltage level translator available in the industry. This allows the device to communicate with advanced processors operating at low-voltage nodes of 0.7 V, 0.8 V, or 0.9 V. The wide VCC range also accommodates the industry standard voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V) commonly found in processors and peripherals. These devices support data rates of up to 380 Mbps while providing 12 mA of drive strength. VCC isolation, IOFF functionality, and built-in ESD (electro static discharge) protection with 8-kV HBM (human body model) and 1-kV CDM (charged device model) are all features standard across this family of devices. Refer to Table 1-1 for information on the AXC family.
PARAMETER | AXC FAMILY |
---|---|
Voltage Support | 0.65 V–3.6 V |
Data Rate | 380 Mbps |
Drive Strength | 12 mA |
Icc (AXC1T at 125°C) | 14 µA |
ESD Ratings | 8-kV HBM, 1-kV CDM |
Operating Temperature | -40°C to 125°C |
Power Sequencing | Not Required |
Ioff Partial power down | Supported |
Most of the devices in the family have a version with bus-hold functionality, denoted by “H” as in AXCH*. Bus hold circuitry allows the voltage translator to retain the last known output state in the event an input becomes high impedance or floating. See the System Consideration for Using Bus-Hold Circuits to Avoid Floating Inputs application report for more information. The 4-bit and 8-bit devices feature two direction control pins allowing two independent banks of buses on a single device. This allows more control in how the device can be provisioned for simultaneous up- and down-translations; and, ideally reduces the BOM count. Additionally, these devices include an output enable pin to put all outputs in a high impedance state which also reduces power consumption. All devices in the family were designed to ensure glitch free power sequencing across hundreds of possible start up or shut down conditions. This allows either supply rail to be powered on or off in any order without causing a glitch at the output. See the Glitch Free Power Sequencing with AXC Level Translators application report.
All microprocessors have General purpose input output (GPIO) ports for communication with the peripheral devices. However, the core and peripheral chips might work at different voltage levels, which is why the system would need a level shifter. If the required signals are not shifted to the voltage at which the microprocessor is operating, it impacts the reliability of communication. The SN74AXC1T45 can be implemented as part of the I/O circuit, especially in single channel signals such as control inputs. The SN74AXC1T45 provides a solution for voltage translating I/O pins such as the following:
Serial peripheral interface (SPI) provides synchronous communication between a processor and peripheral. SPI is a four line “controller-peripheral” architecture communication interface, with three lines driven by the controller (usually the processor) and one line driven by the peripheral (usually the peripheral). Table 2-1 describes the SPI signal interface.
SIGNAL | DESCRIPTION | DIRECTION |
---|---|---|
CLK | Clock Signal | Controller to Peripheral |
CIPO | Controller Input/Peripheral Output | Peripheral to Controller |
COPI | Controller Output/Peripheral Input | Controller to Peripheral |
CS | Peripheral Select | Controller to Peripheral |
The first signal line driven by the controller is CLK, which is the clock signal. With each clock pulse, the controller can transmit or receive one bit to or from the peripheral. The data rate is usually 10 Mbps, however, it can be extended as desired in the system. Since SPI is full duplex, two data lines are needed: COPI and CIPO. COPI stands for controller output peripheral input, and is driven by the controller to send data to the peripheral. CIPO stands for controller input peripheral output, and is driven by the peripheral to send data to the controller. The final line is CS, which is the peripheral select signal. The CS line is driven low by the controller to select the peripheral device for communication. Multiple peripherals may exist in a system and this ensures that the desired peripheral is being communicated with to prevent any system level bus contention. SPI is commonly used in the following:
Interfacing between devices with SPI protocol is possible when the signal levels are the same. In cases where there is a voltage mismatch, it is recommended to use a level shifter. The SN74AXC4T774 or SN74AVC4T774 is the ideal solution to translate all four lines used in SPI. The SN4AXC4T774 has the advantage of each direction of the channel being independently controlled. This makes it extremely useful in SPI where one line operates in the opposite direction from the other three. Additionally, the AXC family can support up to 380 Mbps, which is well above the usual SPI data rates. Since SPI is an interface that can accommodate multiple independent peripherals operating under the same controller, the position of the voltage translator is an important design consideration. In cases where the bus has multiple peripherals each on a different voltage node, it is recommended to put a signal level translator before each peripheral, as opposed to only using one level shifter after the controller as shown in Figure 2-2