SCEA065B November   2018  – March 2021 SN74AVC4T774 , SN74AXC1T45 , SN74AXC4T245 , SN74AXC4T774 , SN74AXC8T245 , SN74AXC8T245-Q1 , SN74AXCH1T45 , SN74AXCH4T245 , SN74AXCH8T245

 

  1.   Trademarks
  2. 1Introduction
  3. 2Common Interfaces and AXC Implementation
    1. 2.1 General Purpose Input Output (GPIO)
    2. 2.2 Serial Peripheral Interface (SPI)
      1. 2.2.1 Voltage Translation for SPI
      2. 2.2.2 SPI Applications
    3.     8
    4. 2.3 UART
      1. 2.3.1 Voltage Translation With UART
      2. 2.3.2 UART Applications
    5. 2.4 Joint Test Action Group (JTAG)
      1. 2.4.1 JTAG Applications
    6. 2.5 Reduced Gigabit Media Independent Interface (RGMII)
      1. 2.5.1 Voltage Translation for RGMII
      2. 2.5.2 RGMII Applications
      3. 2.5.3 Skew Performance
  4. 3Summary
  5. 4Related Documentation
  6. 5Revision History

2.2.1 Voltage Translation for SPI

Interfacing between devices with SPI protocol is possible when the signal levels are the same. In cases where there is a voltage mismatch, it is recommended to use a level shifter. The SN74AXC4T774 or SN74AVC4T774 is the ideal solution to translate all four lines used in SPI. The SN4AXC4T774 has the advantage of each direction of the channel being independently controlled. This makes it extremely useful in SPI where one line operates in the opposite direction from the other three. Additionally, the AXC family can support up to 380 Mbps, which is well above the usual SPI data rates. Since SPI is an interface that can accommodate multiple independent peripherals operating under the same controller, the position of the voltage translator is an important design consideration. In cases where the bus has multiple peripherals each on a different voltage node, it is recommended to put a signal level translator before each peripheral, as opposed to only using one level shifter after the controller as shown in Figure 2-2

GUID-20210319-CA0I-Z1HS-0CKF-MXTCT3SCSS9L-low.svgFigure 2-2 SPI Interface Using SN74AXC4T774 Device