SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

2.4 Data Rate Limitations

Although the number of shift registers connected can be expanded indefinitely, the speed at which data can be loaded into the registers is finite. Each device has a limited maximum clock speed, and data is sent serially from one device to the next, so the total number of bits loaded and the clock frequency applied will affect the total time it takes to read or load the registers. The total time required to load a given number of serial shift registers (tload) can be calculated using Equation 1 with N≔Total registers to load and Fclk≔Shift register clock frequency (Hz).

Equation 1. tload=NFclk

For example, the SN74HCS595 has a maximum clock speed of 60 MHz. If 16 serial shift registers (128 bits total) are to be loaded at this speed, the fastest it can be completed is 2.133 μs. With a more typical clock speed of 1 MHz, the total time to load the same 128 registers would be 128 μs.

Similarly, when loading inputs from multiple parallel-in shift registers such as the SN74HCS165 the same equation can be used. For example, if reading 32 registers (4 devices) with a 100 kHz clock, the time to complete the read would be 320 μs.