SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

2.3 Data Loss Due to Signal Timing

For the majority of systems involving shift registers, delays will be short and no added delays will be required. However, when building a system with many shift registers, especially in larger and more complex systems, timing can become a critical concern. If one shift register in the chain is clocked much earlier than the next, then data can be lost.

Figure 2-3 Example of Configuration That Can Result in Data Loss

Figure 2-3 shows an example scenario in which data can be lost. The initial configuration is shown in the top diagram, with the stored data shown as an alternating pattern, 01010101. The clock signal arrives first at Device 1, which causes all values in Device 1 to shift (to the left in the image). The value in register G is moved to register H (middle diagram). Device 2 does not receive the shift register clock pulse until after the value stored in register H has been overwritten, and thus the value loaded into register A of Device 2 is what was stored in register G of Device 1, and the value that was in register H of Device 1 is lost (bottom diagram). The data, which has been shifted one place to the left, is now 01011101. The fourth bit (counting from the right) has flipped to an incorrect value only because of the timing of the clock inputs.

Figure 2-4 Example of Long Clock Delay That Does Not Result in Data Loss

The solution to this issue is to simply ensure that the clock reaches the devices in the reverse order that data is shifting. By sending the clock to the last device in the chain first, placing added delays in the reverse direction, it can be ensured that no data will be lost.

Figure 2-4 shows an example with this reversed order. The initial state is the same as the first example (top diagram), however the clock arrives to Device 2 first in this scenario. This allows Device 2 to read in the QH’ value from Device 1 before it changes (middle diagram). When the clock finally reaches Device 1, the data is shifted and overwrites the value in register H, however it has already been copied into Device 2 and no data is lost.

This configuration can be used with any number of shift registers. See Section 3 for a detailed design example.