Menu
Product
Email
PDF
Order now
SN74LVC1G11 Single 3-Input Positive-AND Gate
SCES487I
September 2003 – November 2024
SN74LVC1G11
PRODUCTION DATA
CONTENTS
SEARCH
SN74LVC1G11 Single 3-Input Positive-AND Gate
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics, CL = 15 pF
5.7
Switching Characteristics, CL = 30 pF or 50 pF
5.8
Switching Characteristics, CL = 30 pF or 50 pF
5.9
Operating Characteristics
5.10
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support (Analog)
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
search
No matches found.
Full reading width
Full reading width
Comfortable reading width
Expanded reading width
Card for each section
Card with all content
Data Sheet
SN74LVC1G11 Single 3-Input Positive-AND Gate
1
Features
Latch-up performance exceeds 100mA
per JESD 78, class II
ESD protection exceeds JESD 22
±2000V human-body model (A114-A)
±1000V charged-device model (C101)
Available in the Texas Instruments
NanoFree™
package
Supports 5V V
CC
operation
Inputs accept voltages to 5.5V
Maximum t
pd
of 4.1ns at 3.3V
Low power consumption, 10μA maximum I
CC
±24mA output drive at 3.3V
I
off
supports partial-power-down mode operation
