SCES517K December   2003  – November 2023 SN74AVC8T245

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.2 V
    7. 5.7  Switching Characteristics, VCCA = 1.5 V ± 0.1 V
    8. 5.8  Switching Characteristics, VCCA = 1.8 V ± 0.15 V
    9. 5.9  Switching Characteristics, VCCA = 2.5 V ± 0.2 V
    10. 5.10 Switching Characteristics, VCCA = 3.3 V ± 0.3 V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Total Static Power Consumption (ICCA + ICCB)
    13. 5.13 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Fully Configurable Dual-Rail Design
      2. 6.3.2 Support High-Speed Translation
      3. 6.3.3 Ioff Supports Partial-Power-Down Mode Operation
      4. 6.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 6.3.5 Vcc Isolation
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

3 Description

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC8T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. The device is operational with VCCA and VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA.

The SN74AVC8T245 is compatible with a single-supply system and can be replaced later with a '245 function, with minimal printed circuit board redesign.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature allows both ports to be in the high-impedance state when either VCC input is at GND.

To put the device into the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
SN74AVC8T245 RHL (VQFN, 24) 5.5 mm × 3.5 mm
PW (TSSOP, 24) 7.8 mm × 6.4 mm
DGV (TVSOP, 24) 5 mm × 6.4 mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-6A8E2334-22C6-4169-BB0B-CC1AA3DC2B47-low.gif Logic Diagram (Positive Logic)