SCES778B September   2008  – March 2024 SN74AVC16T245-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCCA= 1.2 V
    7. 6.7  Switching Characteristics: VCCA= 1.5 V ± 0.1 V
    8. 6.8  Switching Characteristics: VCCA= 1.8 V ± 0.15 V
    9. 6.9  Switching Characteristics: VCCA= 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics: VCCA= 3.3 V ± 0.3 V
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
      2. 8.3.2 Partial-Power-Down Mode Operation
      3. 8.3.3 VCC Isolation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Enable Times
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

8.3.3 VCC Isolation

The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports are in a high-impedance state (IOZ shown in Section 6.5). This prevents false logic levels from being presented to either bus.