TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to determine that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough so that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by allowing any reflection sees a low impedance at the driver. The O.S. circuits are designed to stay on for approximately 30ns.

The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXS0102V-Q1 device output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.