SCEU030A August   2024  – December 2024 TPLD1201

PRODUCTION DATA  

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Functional Blocks
      1. 2.1.1 Test Points
      2. 2.1.2 Programmer Header Block (P1)
      3. 2.1.3 External Connection Header Block
      4. 2.1.4 GPI Protection Block
      5. 2.1.5 DGS Socket
    2. 2.2 GPIO Testing Blocks
      1. 2.2.1 LED Blocks
      2. 2.2.2 Switch Blocks
      3. 2.2.3 LED/Potentiometer Blocks
  9. 3Software
    1. 3.1 Using the TPLD1201-DGS-EVM
      1. 3.1.1 Equipment Needed for Programming
      2. 3.1.2 Installing Software
    2. 3.2 Configuring a TPLD Device
      1. 3.2.1 TPLD1201-DGS-EVM Setup for Programming
      2. 3.2.2 Inserting a TPLD1201DGS into the DGS Socket
      3. 3.2.3 Connecting the TPLD1201-DGS-EVM to a TPLD-PROGRAM Board
      4. 3.2.4 Temporarily Configuring a TPLD Device
      5. 3.2.5 Permanently Programming a TPLD Device
    3. 3.3 Testing with the TPLD1201-DGS-EVM Demo
      1. 3.3.1 TPLD1201 Demo Circuit
      2. 3.3.2 Testing the Demo
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
      1. 4.2.1 PCB Overview
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Revision History

2.1.1 Test Points

Each GPIO and GPI pin of an socketed TPLD1201DGS part is connected directly to a test point to allow a user to access each pin of the device for probing and testing. The pins are connected to test points as follows:

Pin NumberIO nameTest Point

1

GPI

TP4

2

IO1

TP5

3

IO2TP6

4

IO4TP8

6

IO5

TP10

7

IO6TP11

8

IO7

TP12

9

IO9

TP2

Each test point is connected directly to the corresponding pin, so any disconnected header pins do not disconnect the test points from the pins.