SCHS231E November   1998  – August 2024 CD54AC74 , CD74AC74

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Timing Requirements, VCC = 1.5 V
    7. 4.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
    8. 4.8  Timing Requirements, VCC = 5 V ± 0.5 V
    9. 4.9  Switching Characteristics, VCC = 1.5 V
    10. 4.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    11. 4.11 Switching Characteristics, VCC = 5 V ± 0.5 V
    12. 4.12 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1.     Power Supply Recommendations
    2. 7.1 Layout
      1. 7.1.1 Layout Guidelines
      2. 7.1.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

2 Description

The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
CDx4AC74 J (CDIP, 14) 19.56mm × 7.9mm 19.56mm × 6.67mm
N (PDIP, 14) 19.3mm x 9.4mm 19.3mm x 6.35mm
D (SOIC, 14) 8.65mm x 6mm 8.65mm x 3.9mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
CD54AC74 CD74AC74 Logic Diagram, Each Flip-Flop (Positive Logic) Logic Diagram, Each Flip-Flop (Positive Logic)