2 Configuring Oscillators in TPLD

Oscillators within a TPLD are configurable where the operating frequency can be selected between two options, as shown in Figure 2-1, or fixed to a specific frequency. The operating frequency is fed into a pre-divider and a secondary divider stage to provide a wide range of frequencies that can be used in a TPLD design. The pre-divider stage output is also routed to the clock input of the counter/delay generator macro-cells, where a separate second stage divider is available. For the options available within each device, see the device-specific TPLD data sheets.

The TPLD1201, for example, has one internal oscillator, selectable to operate at 25kHz or at 2MHz. The selected clock then feeds into a pre-divider stage that divides the operating frequency by 1, 2, 4, or 8. The output divider stage provides an additional divide by 1, 2, 3, 4, 8, 12, 24, or 64 option per output. From the output of the pre-divider, the counters have an additional divisor of 1, 4, 12, 24, 64, or 4096 for each counter.

Table 2-1 shows the minimum and maximum frequencies that can be realized at the output of the oscillator and the clocks to drive the counters and/or delay generators in the TPLD1201.