1 What is a State Machine

To understand a state machine we must first define what a state is. A state is a mode of operation that comes with predefined behavior and a trigger condition either transitioning from the state or into the state. That behavior can be a set of outputs expected for example one state can have a logic output of 0010, while another outputs 1011. A state machine (SM) is a system to control a device or program to step through these states. When looking at SM diagrams the circle denotes the state and the behavior of that state is defined either within or below that circle.

The simplest state machine is shown in Figure 1-1.The device sits idle in a power off mode. Once power is applied the device powers on, and outputs 0. Thinking about programs and devices as state machines can often simplify code, and enable easier debugging as the user targets specific states for specific predefined behaviors.

While many state machines are implicit some are explicit. An implicit state machine is one not clearly defined in the design process such as the SM from Figure 1-1. An explicit state machine is one where A great example of explicit state machines can be found in the TPLD family of devices, specifically the TPLD1202. The state machine in the TPLD1202 has eight states, can be used to control eight different outputs per state, and can transition from any single state to another. This state machine can operate as either an asynchronous state machine or a synchronous state machine, and allows for a global reset to bring the state machine to a predefined state at any point during operation.