2 Description

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Device Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾	BODY SIZE⁽³⁾
SN74HC240	DW (SOIC, 20)	12.80mm x 10.3mm	12.80mm x 7.50mm
	DB (SSOP, 20)	7.2mm x 7.8mm	7.2mm x 5.30mm
	DGS (VSSOP, 20)	5.1mm × 4.9mm	5.1mm × 3mm
	PDIP (20)	24.33mm × 9.4mm	24.33mm × 6.35mm
	NS (SOP, 20)	12.6mm x 7.8mm	12.6mm x 5.3mm
	PW (TSSOP, 20)	6.50mm x 6.4mm	6.50mm x 4.40mm
SNx4HC240	J (CDIP, 20)	24.2mm x 7.62mm	24.2 mm x 6.92mm
	FK (LCCC, 20)	8.9mm x 8.9mm	8.9mm x 8.9mm
	W (CFP, 20)	13.09mm x 8.13mm	13.09mm x 6.92mm

(1) For more information, see Mechanical, Packaging, and Orderable Information.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Functional Block Diagram