2 Description

The SNx4AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Device Information

PART NUMBER	PACKAGE ⁽¹⁾	PACKAGE SIZE ⁽²⁾	BODY SIZE ⁽³⁾
SN74AHC138	RGY (VQFN, 16)	4mm x 3.5mm	4mm x 3.5mm
	N (PDIP, 16)	19.3mm × 9.4mm	19.32mm x 6.35 mm
	D (SOIC, 16)	9.9mm × 6mm	9.90mm x 3.90mm
	NS (SOP, 16)	10.2mm x 7.8mm	10.20mm x 5.30mm
	DB (SSOP, 16)	6.2mm × 7.8mm	6.20mm x 5.30mm
	PW (TSSOP , 16)	5mm × 6.4mm	5.00mm x 4.40mm
	DGV (TVSOP, 16)	3.6mm x 6.4mm	3.6mm x 4.4mm

(1) For more information, see Mechanical, Packaging, and Orderable Information.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

(3) The body size (length × width) is a nominal value and does not include pins.

Logic Diagram (Positive Logic)