SCLS259M December   1995  – July 2024 SN74AHC139

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristcs, VCC = 3.3 V ± 0.3 V
    7. 4.7 Switching Characteristics, VCC = 5 V ± 0.5 V
    8. 4.8 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Balanced CMOS 3-State Outputs
      2. 6.3.2 Standard CMOS Inputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Power Considerations
        2. 7.2.1.2 Input Considerations
        3. 7.2.1.3 Output Considerations
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

2 Description

The SN74AHC139 are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74AHC139 D (SOIC, 16) 9.90 mm × 6mm 9.90 mm × 3.90 mm
DB (SSOP, 16) 6.20 mm × 7.8mm 6.20 mm × 5.30 mm
N (PDIP, 16) 19.31 mm × 9.4mm 19.31 mm × 6.35 mm
NS (SOP, 16) 5mm × 6.4mm 5mm × 4.4mm
PW (TSSOP, 16) 5.00 mm × 6.4mm 5.00 mm × 4.40 mm
DGV (TVSOP, 16) 3.6mm × 6.4mm 3.6mm × 4.4mm
RGY (VQFN, 16) 4mm × 3.5mm 4mm × 3.5mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable
(3) The body size (length × width) is a nominal value and does not include pins.
SN74AHC139 Logic Diagram, Each Gate (Positive Logic)
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
Logic Diagram, Each Gate (Positive Logic)